km416s1120d ETC-unknow, km416s1120d Datasheet - Page 20

• Manufacturer Part Number: km416s1120d
• Description: 512k X 16bit X 2 Banks Synchronous Dram Lvttl
• Manufacturer: ETC-unknow

KM416S1120D
8. Burst Stop & Interrupted by Precharge
9. MRS
*Note : 1. t
1) Normal Write (BL=4)
3) Read Interrupted by Precharge (BL=4)
1) Mode Register Set
2. t
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : Both banks precharge if necessary.
Read or write burst stop command is valid at every burst length.
MRS can be issued only at both banks precharge state.
DQ(CL2)
DQ(CL3)
RDL
BDL
DQM
CMD
CMD
CMD
CLK
CLK
CLK
: 1 CLK
: 1 CLK ; Last data in to burst stop delay.
DQ
PRE
WR
RD
D
0
Note 4
D
1
tRP
PRE
D
Q
2
0
tRDL
PRE
MRS
D
Q
Q
Note 1
3
1
0
tMRS = 2CLK
1
Note 3
Q
1
2
ACT
- 20
2) Write Burst Stop (BL=8)
4) Read Burst Stop (BL=4)
DQ(CL3)
DQ(CL2)
CMD
DQM
CMD
CLK
CLK
DQ
WR
RD
D
0
D
1
STOP
D
Q
2
0
CMOS SDRAM
Rev. 1.4 (Jun. 1999)
D
Q
Q
3
1
0
tBDL
1
STOP
D
Note 3
Q
Note 2
4
1
2
D
5