km416s1120d ETC-unknow, km416s1120d Datasheet - Page 30

• Manufacturer Part Number: km416s1120d
• Description: 512k X 16bit X 2 Banks Synchronous Dram Lvttl
• Manufacturer: ETC-unknow

DQ
CLOCK
KM416S1120D
Page Read & Write Cycle at Same Bank @Burst Length=4
A
ADDR
DQM
10
CKE
RAS
CAS
/AP
WE
CS
BA
CL=2
CL=3
*Note :
0
Row Active
(A-Bank)
Ra
Ra
1
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
2. Row precharge will interrupt writing. Last data input, t
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
command to avoid bus contention.
before end of burst. Input data after Row precharge cycle will be masked internally.
2
tRCD
3
(A-Bank)
Read
Ca0
4
5
(A-Bank)
Read
Cb0
Qa0
6
Qa1
Qa0
7
Qb0
Qa1
8
Qb0
Qb1 Qb2
- 30
*Note 1
9
RDL
HIGH
Qb1
before Row precharge, will be written.
10
11
(A-Bank)
Write
Dc0
Dc0
Cc0
tCDL
12
Dc1
Dc1
13
(A-Bank)
Write
Cd0
Dd0
Dd0
14
Dd1
Dd1
15
tRDL
Precharge
(A-Bank)
*Note 2
*Note 3
CMOS SDRAM
Rev. 1.4 (Jun. 1999)
16
17
18
: Don't care
19