km416s1120d ETC-unknow, km416s1120d Datasheet - Page 31

• Manufacturer Part Number: km416s1120d
• Description: 512k X 16bit X 2 Banks Synchronous Dram Lvttl
• Manufacturer: ETC-unknow

DQ
CLOCK
KM416S1120D
Page Read Cycle at Different Bank @Burst Length=4
A
ADDR
DQM
10
CKE
RAS
CAS
/AP
WE
CS
BA
CL=2
CL=3
*Note :
0
*Note 1
Row Active
(A-Bank)
RAa
RAa
1
1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
2
(A-Bank)
Read
CAa
3
Row Active
(B-Bank)
RBb
RBb
4
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1
5
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1
6
(B-Bank)
Read
CBb
7
8
- 31
9
HIGH
10
(A-Bank)
Read
CAc
11
12
(B-Bank)
Read
CBd
13
14
(A-Bank)
Read
QBd0 QBd1 QAe0 QAe1
CAe
15
QBd0 QBd1 QAe0 QAe1
CMOS SDRAM
Rev. 1.4 (Jun. 1999)
16
Precharge
(A-Bank)
*Note 2
17
18
: Don't care
19