z8e001 ZiLOG Semiconductor, z8e001 Datasheet - Page 28

• Manufacturer Part Number: z8e001
• Description: Feature-rich Z8plus One-time Programmable Otp Microcontroller
• Manufacturer: ZiLOG Semiconductor

Z8E001
Z8Plus OTP Microcontroller
TIMERS (Continued)
at any time, and will have no effect on the functionality of
the timer.
If a timer pair is defined to operate as a single 16-bit entity,
the entire 16-bit value must reach 0 before an interrupt is
generated. In this case, a single interrupt is generated, and
the interrupt corresponds to the even 8-bit timer.
Example: Timers T2 and T3 are cascaded to form a single 16-
In parallel with the posting of the interrupt request, the in-
terrupting timerÕs count value is initialized by copying the
contents of the auto-initialization value register to the count
value register. It should be noted that any time that a timer
pair is defined to act as a single 16-bit timer, that the auto-
reload function is performed automatically. All 16-bit tim-
ers continue counting while their interrupt requests are ac-
tive, and each operates in a free-running manner.
If interrupts are disabled for a long period of time, it is pos-
sible for the timer to decrement to 0 again before its initial
interrupt has been responded to. This condition is termed a
degenerate case, and hardware is not required to detect it.
When the timer control register is written, all timers that are
enabled by the write begins counting using the value that
is held in the count register. In this case, an auto-initializa-
tion is not performed. All timers can receive an internal
clock source only. Each timer that is enabled is updated ev-
ery 8th XTAL clock cycle.
If T0 and T1 are defined to work independently, then each
works as an 8-bit timer with a single auto-initialization reg-
ister (T0ARLO for T0, and T1ARLO for T1). Each timer
asserts its predefined interrupt when it times out, optionally
performing the auto-initialization function. If T0 and T1 are
cascaded to form a single 16-bit timer, then the single 16-
bit timer is capable of performing as a Pulse-Width Mod-
ulator (PWM). This timer is referred to as T01 to distinguish
it as having special functionality that is not available when
T0 and T1 act independently.
When T01 is enabled, it can use a pair of 16-bit auto-ini-
tialization registers. In this mode, one 16-bit auto-initial-
ization value is composed of the concatenation of T1ARLO
and T0ARLO. The second auto-initialization value is com-
posed of the concatenation of T1ARHI and T0ARHI. When
28
bit timer, so the interrupt for the combined timer is
defined to be that of timer T2 rather than T3. When
a timer pair is specified to act as a single 16-bit
timer, the even timer registers in the pair (timer T0
or T2) is defined to hold the timerÕs least significant
byte. In contrast, the odd timer in the pair holds the
timerÕs most significant byte.
P R E L I M I N A R Y
T01 times out, it alternately initializes its count value using
the LO auto-init pair, followed by the HI auto-init pair. This
functionality corresponds to a PWM, where the T1 interrupt
defines the end of the HI section of the waveform, and the
T0 interrupt marks the end of the LO portion of the PWM
waveform.
To use the cascaded timers as a PWM, one must initialize
the T0 and T1 count registers to work in conjunction with
the port pin. The user should initialize the T0 and T1 count
registers to the PWM_HI auto-init value to obtain the re-
quired PWM behavior. The PWM is arbitrarily defined to
use the LO autoreload registers first, implying that it had
just timed out after beginning in the HI portion of the PWM
waveform. As such, the PWM is defined to assert the T1
interrupt after the first timeout interval.
After the auto-initialization has been completed, decre-
menting occurs for the number of counts defined by the
PWM_LO registers. When decrementing again reaches 0,
the T0 interrupt is asserted; and auto-init using the
PWM_HI registers occurs. Decrementing occurs for the
number of counts defined by the PWM_HI registers until
reaching 0. From there, the T1 interrupt is asserted, and the
cycle begins again.
The internal timers can be used to trigger external events
by toggling the PB1 output when generating an interrupt.
This functionality can only be achieved in conjunction with
the port unit defining the appropriate pin as an output signal
with the timer output special function enabled. In this mode,
the appropriate port output is toggled when the timer count
reaches 0, and continues toggling each time that the timer
times out.
T
The PortB special function register PTBSFR (0D7H) (Fig-
ure 23) is used in conjunction with the Port B directional
control register PTBDIR (0D6) (Figure 24) to configure
PB1 for T
function, PB1 must be defined as an output line by setting
PTBDIR bit 1 to 1. Configured in this way, PB1 has the ca-
pability of being a clock output for timer0, toggling the PB1
output pin on each timer0 timeout.
At end-of-count, the interrupt request line IRQ0, clocks a
toggle flip-flop. The output of this flip-flop drives the T
line, PB1. In all cases, when timer0 reaches its end-of-count,
T
ample, timer0 is in Continuous Counting Mode, T
a 50 percent duty cycle output. This duty cycle can easily
be controlled by varying the initial values after each end-
of-count.
OUT
OUT
toggles to its opposite state (Figure 25). If, for ex-
Mode
OUT
operation for timer0. In order for T
DS001101-Z8X0400
OUT
ZiLOG
OUT
OUT
has
to