z8e001 ZiLOG Semiconductor, z8e001 Datasheet - Page 19

• Manufacturer Part Number: z8e001
• Description: Feature-rich Z8plus One-time Programmable Otp Microcontroller
• Manufacturer: ZiLOG Semiconductor

ZiLOG
Z8E001 WATCH-DOG TIMER (WDT)
The WDT is a retriggerable one-shot 16-bit timer that resets
the Z8E001 if it reaches its terminal count. The WDT is driv-
en by the XTAL2 clock pin. To provide the longer timeout
periods required in applications, the watchdog timer is only
updated every 64th clock cycle. When operating in the RUN
or HALT Modes, a WDT timeout reset is functionally
equivalent to an interrupt vectoring the PC to 0020H and
setting the WDT flag to a one state. Coming out of RESET,
the WDT is fully enabled with its timeout value set at the
maximum value, unless otherwise programmed during the
first instruction. Subsequent executions of the WDT in-
struction, reinitialize the watchdog timer registers (C2H and
C3H), to their initial values as defined by bits D6, D5, and
D4 of the TCTLHI register. The WDT cannot be disabled
except on the first cycle after RESET, and if the device en-
ters Stop mode.
The WDT instruction should be executed often enough to
provide some margin before allowing the WDT registers to
DS001101-Z8X0400
0C1
D7
*Designates Default Value after RESET
D6
D5
Figure 12. Z8E001 TCTLHI Register for Control of WDT
D4
TCTLHI
D3
D2
P R E L I M I N A R Y
D1
get near 0. Because the WDT timeout periods are relatively
long, a WDT reset will occur in the unlikely event that the
WDT times out on exactly the same cycle that the WDT in-
struction is executed.
The WDT and SMR flags are the only flags that are affected
by the external RESET pin. RESET clears both the WDT
and SMR flags. A WDT timeout sets the WDT flag. The
STOP instruction sets the SMR flag. This behavior enables
software to determine whether a pin RESET occurred, or
whether a WDT timeout occurred, or whether a return from
STOP Mode occurred. Reading the WDT and SMR flags
does not reset it to zero, the user must clear it via software.
Note: Failure to clear the SMR flag can result in undefined be-
D0
havior.
RESERVED (MUST BE 0)
0 = STOP MODE ENABLED
1 = STOP MODE DISABLED*
D6 D5 D4 WDT TIMEOUT VALUE
---- ---- ---- --------------------------------
(XTAL CLOCKS TO TIMEOUT)
0
0
0
0
1
1
1
1
1 = WDT ENABLED IN HALT MODE*
0 = WDT DISABLED IN HALT MODE
0
0
1
1
0
0
1
1
0
1
0
1
0
1 1,048,576 TpC
0 2,097,152 TpC
1 4,194,304 TpC*
Z8Plus OTP Microcontroller
DISABLED
131,072 TpC
262,144 TpC
524,288 TpC
65,536 TpC
Z8E001
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