z8e001 ZiLOG Semiconductor, z8e001 Datasheet - Page 21

• Manufacturer Part Number: z8e001
• Description: Feature-rich Z8plus One-time Programmable Otp Microcontroller
• Manufacturer: ZiLOG Semiconductor

ZiLOG
STOP MODE OPERATION
The STOP Mode provides the lowest possible device stand-
by current. This instruction turns off the on-chip oscillator
and internal system clock.
To enter the STOP Mode, the Z8E001 only requires a STOP
instruction. It is NOT necessary to execute a NOP instruc-
tion immediately before the STOP instruction.
The STOP Mode is exited by any one of the following re-
sets: RESET pin or a STOP-Mode Recovery source. Upon
reset generation, the processor always restarts the applica-
tion program at address 0020H, and the STOP Mode Flag
is set. Reading the STOP Mode Flag does not clear it. The
user must clear the STOP Mode Flag with software.
Note: Failure to clear the STOP Mode Flag can result in unde-
CLOCK
The Z8E001 MCU derives its timing from on-board clock
circuitry connected to pins XTAL1 and XTAL2. The clock
circuitry consists of an oscillator, a glitch filter, a divide-
by-two shaping circuit, a divide-by-four shaping circuit,
and a divide-by-eight shaping circuit. Figure 13 illustrates
the clock circuitry. The oscillatorÕs input is XTAL1 and its
output is XTAL2. The clock can be driven by a crystal, a
ceramic resonator, LC clock, or an external clock source.
DS001101-Z8X0400
6F
fined behavior.
STOP
;enter STOP Mode
P R E L I M I N A R Y
The Z8E001 provides a dedicated STOP-Mode Recovery
(SMR) circuit. In this case, a low-level applied to input pin
PB0 triggers an SMR. To use this mode, pin PB0 (I/O Port
B, bit 0) must be configured as an input before the STOP
Mode is entered. The Low level on PB0 must be held for a
minimum pulse width T
time. Program execution starts at address 20Hex after PB0
is raised back to a high level.
Notes: Use of the PB0 input for the stop mode recovery does
XTAL2
XTAL1
not initialize the control registers.
The STOP Mode current (I
•
•
•
V
Output current sourcing is minimized.
All inputs (digital and analog) are at the Low or
High rail voltages.
Figure 13. Z8E001 Clock Circuit
CC
is at the low end of the devices operating range.
Glitch
WSM
Filter
Z8Plus OTP Microcontroller
plus any oscillator startup
CC2
) is minimized when:
2
4
8
Machine
Clock
(5 cycles
per in-
struction)
WDT
Clock
Timer
Clock
Z8E001
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