z8e001 ZiLOG Semiconductor, z8e001 Datasheet - Page 20

• Manufacturer Part Number: z8e001
• Description: Feature-rich Z8plus One-time Programmable Otp Microcontroller
• Manufacturer: ZiLOG Semiconductor

Z8E001
Z8Plus OTP Microcontroller
Note: The WDT can only be disabled via software if the first
The TCTLHI bits for control of the WDT are described be-
low:
WDT Time Select (D6, D5, D4).
the time-out period. Table 6 indicates the range of timeout
values that can be obtained. The default values of D6, D5,
and D4 are all 1, thus setting the WDT to its maximum tim-
eout period when coming out of RESET.
WDT During HALT (D7).
not the WDT is active during HALT Mode. A 1 indicates
active during HALT. A 0 prevents the WDT from resetting
the part while halted.Coming out of reset, the WDT is en-
abled during HALT Mode.
POWER-DOWN MODES
I
ports two Power-Down modes to minimize device current con-
sumption. The two modes supported are
HALT MODE OPERATION
The HALT Mode suspends instruction execution and turns
off the internal CPU clock. The on-chip oscillator circuit
remains active so the internal clock continues to run and is
applied to the timers and interrupt logic.
To enter the HALT Mode, the Z8E001 only requires a
HALT instruction. It is NOT necessary to execute a NOP
instruction immediately before the HALT instruction.
20
n addition to the standard RUN mode, the Z8
7F
instruction out of RESET performs this function. Logic
within the Z8E001 detects that it is in the process of ex-
ecuting the first instruction after the part leaves RESET.
During the execution of this instruction, the upper five
bits of the TCTLHI register can be written. After this
first instruction, hardware does not allow the upper five
bits of this register to be written.
HALT
This bit determines whether or
; enter HALT Mode
Bits 6, 5, and 4 determine
HALT and STOP.
E001
MCU sup-
P R E L I M I N A R Y
STOP MODE (D3).
STOP Mode is disabled. If an application requires use of
STOP Mode, bit D3 must be cleared immediately upon
leaving RESET. If bit D3 is set, the STOP instruction exe-
cutes as a NOP. If bit D3 is cleared, the STOP instruction
enters Stop Mode. Whenever the Z8E001 wakes up after
having been in STOP Mode, the STOP Mode is again dis-
abled.
Bits 2, 1 and 0.
The HALT Mode can be exited by servicing an interrupt
(either externally or internally) generated. Upon comple-
tion of the interrupt service routine, the user program con-
tinues from the instruction after the HALT instruction.
The HALT Mode can also be exited via a RESET activation
or a Watch-Dog Timer (WDT) timeout. In these cases, pro-
gram execution restarts at the reset restart address 0020H.
D6
0
0
0
0
1
1
1
1
Note:
*
TpC=XTAL clock cycle. The default on reset is D6=D5=D4=1.
D5
0
0
1
1
0
0
1
1
D4
0
1
0
1
0
1
0
1
These bits are reserved and must be 0.
Table 6. WDT Time-Out
Crystal Clocks*
to Timeout
Disabled
65,536 TpC
131,072 TpC
262,144 TpC
524,288 TpC
1,048,576 TpC
2,097,152 TpC
4,194,304 TpC
Coming out of RESET, the Z8E001
DS001101-Z8X0400
Time-Out Using
a 10 MHZ Crystal
Disabled
6.55 ms
13.11 ms
26.21 ms
52.43 ms
104.86 ms
209.72 ms
419.43 ms
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