r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 539
r5f21346mnfp
Manufacturer Part Number
r5f21346mnfp
Description
Single-chip Mcus Incorporates The R8c Cpu Core
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5F21346MNFP.pdf
(776 pages)
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R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
25.3
25.3.1
25.3.1.1
The transfer clock can be selected from among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8,
and f1/4) and an external clock.
When using synchronous serial communication unit, set the SCKS bit in the SSMR2 register to 1 and select the
SSCK pin as the serial clock pin.
When the MSS bit in the SSCRH register is set to 1 (operates as master device), an internal clock can be
selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs clocks of the
transfer rate selected by bits CKS0 to CKS2 in the SSCRH register.
When the MSS bit in the SSCRH register is set to 0 (operates as slave device), an external clock can be selected
and the SSCK pin functions as input.
The association between the transfer clock polarity, phase and data changes according to the combination of the
SSUMS bit in the SSMR2 register and bits CPHS and CPOS in the SSMR register.
Figure 25.2 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data.
Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register.
When the MLS bit is set to 1, transfer is started from the LSB and proceeds to the MSB. When the MLS bit is
set to 0, transfer is started from the MSB and proceeds to the LSB.
Common Items for Multiple Modes
Transfer Clock
Association between Transfer Clock Polarity, Phase, and Data
25. Synchronous Serial Communication Unit (SSU)
Page 507 of 740
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