r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 21

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

26.
25.4
25.5
25.6
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
25.3.3
25.3.4
25.4.1
25.4.2
25.4.3
25.5.1
25.5.2
25.5.3
25.5.4
26.2.1
26.2.2
26.2.3
26.2.4
26.2.5
26.2.6
26.2.7
26.2.8
26.2.9
26.2.10 IIC bus Status Register (ICSR) ......................................................................................................... 537
26.2.11 Slave Address Register (SAR) .......................................................................................................... 538
26.2.12 IIC bus Shift Register (ICDRS) ........................................................................................................ 538
26.3.1
26.3.2
26.3.3
26.4.1
26.4.2
26.4.3
26.4.4
26.4.5
26.5.1
26.5.2
26.5.3
26.9.1
26.9.2
I
2
C bus Interface ......................................................................................................................... 527
Clock Synchronous Communication Mode .......................................................................................... 512
Operation in 4-Wire Bus Communication Mode .................................................................................. 519
Notes on Synchronous Serial Communication Unit .............................................................................. 526
Overview ............................................................................................................................................... 527
Registers ................................................................................................................................................ 530
Common Items for Multiple Modes ...................................................................................................... 539
I
Clock Synchronous Serial Mode ........................................................................................................... 554
Examples of Register Setting ................................................................................................................ 557
Noise Canceller ..................................................................................................................................... 561
Bit Synchronization Circuit ................................................................................................................... 562
Notes on I
2
C bus Interface Mode ......................................................................................................................... 543
Interrupt Requests ............................................................................................................................. 510
Communication Modes and Pin Functions ....................................................................................... 511
Initialization in Clock Synchronous Communication Mode ............................................................ 512
Data Transmission ............................................................................................................................ 513
Data Reception .................................................................................................................................. 515
Initialization in 4-Wire Bus Communication Mode ......................................................................... 520
Data Transmission ............................................................................................................................ 521
Data Reception .................................................................................................................................. 523
SCS Pin Control and Arbitration ...................................................................................................... 525
Module Standby Control Register (MSTCR) ................................................................................... 530
SSU/IIC Pin Select Register (SSUIICSR) ........................................................................................ 530
I/O Function Pin Select Register (PINSR) ....................................................................................... 531
IIC bus Transmit Data Register (ICDRT) ......................................................................................... 532
IIC bus Receive Data Register (ICDRR) .......................................................................................... 532
IIC bus Control Register 1 (ICCR1) ................................................................................................. 533
IIC bus Control Register 2 (ICCR2) ................................................................................................. 534
IIC bus Mode Register (ICMR) ........................................................................................................ 535
IIC bus Interrupt Enable Register (ICIER) ....................................................................................... 536
Transfer Clock .................................................................................................................................. 539
SDA Pin Digital Delay Selection ...................................................................................................... 541
Interrupt Requests ............................................................................................................................. 542
I2C bus Format ................................................................................................................................. 543
Master Transmit Operation ............................................................................................................... 544
Master Receive Operation ................................................................................................................ 546
Slave Transmit Operation ................................................................................................................. 549
Slave Receive Operation ................................................................................................................... 552
Clock Synchronous Serial Format .................................................................................................... 554
Transmit Operation ........................................................................................................................... 555
Receive Operation ............................................................................................................................. 556
Master Receive Mode ....................................................................................................................... 563
The ICE Bit in the ICCR1 Register and the IICRST Bit in the ICCR2 Register ............................. 563
2
C bus Interface .................................................................................................................... 563
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