r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 509

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
23.5
Table 23.9
Notes:
Transfer data format
Transfer clock
Transmit start conditions
Receive start conditions
Interrupt request generation
timing
Error detection
Selectable functions
I
Specifications. Tables 23.10 and 23.11 list the registers used in I
Mode Functions, Figure 23.13 shows an I
Register and Interrupt Timing.
As shown in Table 23.12, the MCU is placed in I
to 1. Because SDA2 transmit output has a delay circuit attached, SDA2 output does not change state until SCL2
goes low and remains stably low.
2
1. When an external clock is selected, the requirements must be met while the external clock is held high.
2. If an overrun error occurs, the received data in the U2RB register will be undefined. The IR bit in the S2RIC
C mode is provided for use as a simplified I
register remains unchanged.
Special Mode 1 (I
Item
I
2
C Mode Specifications
2
Transfer data length: 8 bits
• Master mode
• Slave mode
To start transmission, the following requirements must be met:
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register).
To start reception, the following requirements must be met:
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register).
Start/stop condition detection, no acknowledgement detection, or acknowledgement
detection
Overrun error
• SDA2 digital delay
• Clock phase setting
C Mode)
The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(2(n+1))
fj = f1, f8, f32, fC n = setting value in the U2BRG register: 00h to FFh
The CKDIR bit is set to 1 (external clock): Input from the SCL2 pin
No digital delay or a delay of 2 to 8 U2BRG count source clock cycles
can be selected.
With or without clock delay can be selected.
This error occurs if the serial interface starts receiving the next unit of data before
reading the U2RB register and receives the 8th bit of the next unit of data.
2
C Mode Block Diagram, and Figure 23.14 shows the Transfer to U2RB
(2)
2
2
C mode by setting bits SMD2 to SMD0 to 010b and the IICM bit
C interface compatible mode. Table 23.9 lists the I
2
C mode and the settings. Table 23.12 lists the I
Specification
23. Serial Interface (UART2)
(1)
(1)
Page 477 of 740
2
C Mode
2
C