mc56f801 Freescale Semiconductor, Inc, mc56f801 Datasheet - Page 70

• Manufacturer Part Number: mc56f801
• Description: 16-bit Digital Signal Controllers
• Manufacturer: Freescale Semiconductor, Inc

6.3.8
All of the peripheral pins on the 56F8014 share their Input/Output (I/O) with GPIO ports. In order to select
peripheral or GPIO control, program the GPIOx_PEREN register. In some cases, there are two possible
peripherals as well as the GPIO functionality available for control of the I/O. In these cases, the SIM_GPS
register is used to determine which peripheral has control.
As shown in
pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O when
PEREN = 1.
6.3.8.1
This bit selects the clock speed for the TMR module.
Note: This bit should only be changed while the TMR module’s clock is disabled. See
Note: High-speed clocking is only available when the PLL is being used.
Note: If the PWM reload pulse is used as input to Timer 3 (See SIM_CTRL: TC3_INP,
then the clocks of the Quad Timer and PWM must be related, as shown in
70
•
•
Base + $B
RESET
0 = TMR module clock rate equals core clock rate, typically 32MHz (default)
1 = TMR module clock rate equals three times core clock rate
Write
Read
SIM GPIO Peripheral Select Register (SIM_GPS)
TMR Clock Rate (TCR)—Bit 15
Figure
TCR
15
0
Figure 6-9 Overall Control of Pads Using SIM_GPS Control
Figure 6-10 GPIO Peripheral Select Register (SIM_GPS)
6-9, the GPIO Peripheral Enable Register (PEREN) has the final control over which
PCR
14
Quad Timer Controlled
0
13
0
0
SCI Controlled
12
0
0
SIM_GPS Register
CFG_
11
B7
0
56F8014 Technical Data, Rev. 9
GPIO Controlled
CFG_
10
B6
0
CFG_
B5
9
0
0
1
GPIOB_PEREN Register
CFG_
B4
8
0
CFG_
B3
7
0
0
1
CFG_
B2
6
0
I/O Pad Control
CFG_
B1
5
0
Table
CFG_
B0
4
0
6-2.
3
0
CFG_A5
Freescale Semiconductor
2
0
Section
Section
1
0
CFG_A4
Preliminary
6.3.9.
6.3.1.7),
0
0