mc56f801 Freescale Semiconductor, Inc, mc56f801 Datasheet - Page 61

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mc56f801

Manufacturer Part Number
mc56f801
Description
16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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5.7 Resets
5.7.1
5.7.2
5.7.2.1
The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is
asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET
is released. The general timing is shown in
5.7.3
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,
except the core IRQs with fixed priorities:
These interrupts are enabled at their fixed priority levels.
Freescale Semiconductor
Preliminary
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
SW Interrupt LP
RES
CLK
General
Description of Reset Operation
VAB
PAB
ITCN After Reset
Core Reset
Reset Handshake Timing
Reset
Priority
Figure 5-19 Reset Interface
Table 5-4 Reset Summary
56F8014 Technical Data, Rev. 9
Figure 5-19
RESET_VECTOR_ADR
Source
RST
.
Core reset from the SIM
Characteristics
READ_ADR
Resets
61

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