at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 90

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Figure 14-6. User Reset State
14.3.4.4
90
periph_nreset
proc_nreset
(nrst_out)
RSTTYP
AT91SAM9G20 Preliminary
NRST
SLCK
NRST
MCK
Software Reset
When the processor reset signal is released, the RSTTYP field of the Status Register
(RSTC_SR) is loaded with the value 0x4, indicating a User Reset.
T h e
EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How-
ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low
externally, the internal reset lines remain asserted until NRST actually rises.
The Reset Controller offers several commands used to assert the different reset signals. These
commands are performed by writing the Control Register (RSTC_CR) with the following bits at
1:
The software reset is entered if at least one of these bits is set by the software. All these com-
mands can be performed independently or simultaneously. The software reset lasts 3 Slow
Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is
detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; syn-
chronously to SLCK.
• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory
• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field
Resynch.
2 cycles
Any
Freq.
Any
system, and, in particular, the Remap Command. The Peripheral Reset is generally used for
debug purposes.
ERSTL in the Mode Register (RSTC_MR).
N R S T
>= EXTERNAL RESET LENGTH
M a n a g e r
g u a r a n t e e s
Resynch.
2 cycles
XXX
t h a t
t h e
Processor Startup
= 3 cycles
N R S T
l i n e
0x4 = User Reset
i s
6384B–ATARM–15-Dec-08
a s s e r t e d
f o r