at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 28

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Note:
10.2.1
10.2.1.1
10.2.1.2
10.3
28
Setting AIC, SYSC, UHP, ADC and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect. The ADC clock is auto-
matically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion.
Peripheral Signal Multiplexing on I/O Lines
AT91SAM9G20 Preliminary
Peripheral Interrupts and Clock Control
System Interrupt
External Interrupts
Table 10-1.
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to
IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these
peripheral IDs.
The AT91SAM9G20 features 3 PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines
of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral
functions, A or B.
define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The
two columns “Function” and “Comments” have been inserted in this table for the user’s own
comments; they may be used to track how pins are defined in an application.
Note that some peripheral functions which are output only might be duplicated within both
tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral
mode. If I/O appears, the PIO Line resets in input with the pull-up enabled, so that the device is
maintained in a static state as soon as the reset is released. As a result, the bit corresponding to
the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name appears in the “Reset State” column, the PIO Line is assigned to this function
and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories,
in particular the address lines, which require the pin to be driven as soon as the reset is
released. Note that the pull-up resistor is also enabled in this case.
Peripheral ID
29
30
31
• the SDRAM Controller
• the Debug Unit
• the Periodic Interval Timer
• the Real-time Timer
• the Watchdog Timer
• the Reset Controller
• the Power Management Controller
AT91SAM9G20 Peripheral Identifiers (Continued)
Table 10-2 on page
Peripheral Mnemonic
AIC
AIC
AIC
29,
Table 10-3 on page 30
Peripheral Name
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
and
Table 10-4 on page 31
6384B–ATARM–15-Dec-08
External Interrupt
IRQ0
IRQ1
IRQ2