at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 287

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

6384B–ATARM–15-Dec-08
4. Setting PLL B and divider B:
5. Selection of Master Clock and Processor Clock
PLL A input clock is main clock divided by 2. PLL An output clock is PLL A input clock multi-
plied by 4. Once CKGR_PLLAR has been written, LOCKA bit will be set after six slow clock
cycles.
All parameters needed to configure PLL B and divider B are located in the CKGR_PLLBR
register.
The DIVB field is used to control divider B itself. A value between 0 and 255 can be pro-
grammed. Divider B output is divider B input divided by DIVB parameter. By default DIVB
parameter is set to 0 which means that divider B is turned off.
The OUTB field is used to select the PLL B output frequency range.
The MULB field is the PLL B multiplier factor. This parameter can be programmed between
0 and 62. If MULB is set to 0, PLL B will be turned off, otherwise the PLL B output frequency
is PLL B input frequency multiplied by (MULB + 1).
The PLLBCOUNT field specifies the number of slow clock cycles before LOCKB bit is set in
the PMC_SR register after CKGR_PLLBR register has been written.
Once the PMC_PLLB register has been written, the user must wait for the LOCKB bit to be
set in the PMC_SR register. This can be done either by polling the status register or by wait-
ing the interrupt line to be raised if the associated interrupt to LOCKB has been enabled in
the PMC_IER register. All parameters in CKGR_PLLBR can be programmed in a single
write operation. If at some stage one of the following parameters, MULB, DIVB is modified,
LOCKB bit will go low to indicate that PLL B is not ready yet. When PLL B is locked, LOCKB
will be set again. The user is constrained to wait for LOCKB bit to be set before using the
PLL A output clock.
The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the
USB clock(s).
Code Example:
PLL B input clock is main clock divided by 2. PLL B output clock is PLL B input clock multi-
plied by 4. Once CKGR_PLLBR has been written, LOCKB bit will be set after six slow clock
cycles.
The Master Clock and the Processor Clock are configurable via the PMC_MCKR register.
The CSS field is used to select the clock source of the Master Clock and Processor Clock
dividers. By default, the selected clock source is slow clock.
The PRES field is used to control the Master/Processor Clock prescaler. The user can
choose between different values (1, 2, 4, 8, 16, 32, 64). Prescaler output is the selected
clock source divided by PRES parameter. By default, PRES parameter is set to 1 which
means that the input clock of the Master Clock and Processor Clock dividers is equal to slow
clock.
write_register(CKGR_PLLBR,0x20030602)
AT91SAM9G20 Preliminary
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