dspic33fj16gs404t-i-pt Microchip Technology Inc., dspic33fj16gs404t-i-pt Datasheet - Page 256

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dspic33fj16gs404t-i-pt

Manufacturer Part Number
dspic33fj16gs404t-i-pt
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 19-7:
DS70318D-page 254
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
Note 1: This register is only implemented on the dsPIC33FJ16GS504 devices.
IRQEN5
IRQEN4
R/W-0
R/W-0
2: If other conversions are in progress, then conversion will be performed when the conversion resources are
available.
IRQEN5: Interrupt Request Enable 5 bit
1 = Enable IRQ generation when requested conversion of channels AN11 and AN10 is completed
0 = IRQ is not generated
PEND5: Pending Conversion Status 5 bit
1 = Conversion of channels AN11 and AN10 is pending; set when selected trigger is asserted
0 = Conversion is complete
SWTRG5: Software Trigger 5 bit
1 = Start conversion of AN11 and AN10 (if selected in TRGSRC bits)
This bit is automatically cleared by hardware when the PEND5 bit is set.
0 = Conversion is not started
PEND5
PEND4
R/W-0
R/W-0
ADCPC2: A/D CONVERT PAIR CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
SWTRG5
SWTRG4
R/W-0
R/W-0
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
TRGSRC5<4:0>
TRGSRC4<4:0>
R/W-0
R/W-0
(2)
© 2009 Microchip Technology Inc.
(1)
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0

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