dspic33fj16gs404t-i-pt Microchip Technology Inc., dspic33fj16gs404t-i-pt Datasheet - Page 140

• Manufacturer Part Number: dspic33fj16gs404t-i-pt
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 8-1:
DS70318D-page 138
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-12
bit 11
bit 10-8
bit 7
bit 6
bit 5
bit 4
CLKLOCK
Note 1: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillator (Part IV)” (DS70307)
R/W-0
U-0
—
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
in the “dsPIC33F Family Reference Manual” (available from the Microchip website) for details.
This applies to clock switches in either direction. In these instances, the application must switch to FRC mode
as a transition clock source between the two PLL modes.
Unimplemented: Read as ‘0’
COSC<2:0>: Current Oscillator Selection bits (read-only)
000 = Fast RC oscillator (FRC)
001 = Fast RC oscillator (FRC) with PLL
010 = Primary oscillator (XT, HS, EC)
011 = Primary oscillator (XT, HS, EC) with PLL
100 = Reserved
101 = Low-Power RC oscillator (LPRC)
110 = Fast RC oscillator (FRC) with divide-by-16
111 = Fast RC oscillator (FRC) with divide-by-n
Unimplemented: Read as ‘0’
NOSC<2:0>: New Oscillator Selection bits
000 = Fast RC oscillator (FRC)
001 = Fast RC oscillator (FRC) with PLL
010 = Primary oscillator (XT, HS, EC)
011 = Primary oscillator (XT, HS, EC) with PLL
100 = Reserved
101 = Low-Power RC oscillator (LPRC)
110 = Fast RC oscillator (FRC) with divide-by-16
111 = Fast RC oscillator (FRC) with divide-by-n
CLKLOCK: Clock Lock Enable bit
If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01):
1 = Clock switching is disabled, system clock source is locked
0 = Clock switching is enabled, system clock source can be modified by clock switching
IOLOCK: Peripheral Pin Select Lock bit
1 = Peripherial pin select is locked, write to Peripheral Pin Select registers not allowed
0 = Peripherial pin select is not locked, write to Peripheral Pin Select registers allowed
LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
Unimplemented: Read as ‘0’
IOLOCK
R/W-0
R-0
OSCCON: OSCILLATOR CONTROL REGISTER
COSC<2:0>
y = Value set from Configuration bits on POR
W = Writable bit
‘1’ = Bit is set
LOCK
R-0
R-0
R-0
U-0
Preliminary
—
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/C-0
U-0
CF
—
R/W-y
(1)
U-0
—
© 2009 Microchip Technology Inc.
NOSC<2:0>
x = Bit is unknown
R/W-y
U-0
—
(2)
OSWEN
R/W-y
R/W-0
bit 8
bit 0