dspic33fj16gs404t-i-pt Microchip Technology Inc., dspic33fj16gs404t-i-pt Datasheet - Page 247

• Manufacturer Part Number: dspic33fj16gs404t-i-pt
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

REGISTER 19-1:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
Note 1: This control bit can only be changed while ADC is disabled (ADON = 0), and only applies to single SAR
R/W-0
ADON
R/W-0
EIE
(1)
devices.
ADON: A/D Operating Mode bit
1 = A/D converter module is operating
0 = A/D converter is off
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
SLOWCLK: Enable The Slow Clock Divider bit
1 = ADC is clocked by the auxiliary PLL (ACLK)
0 = ADC is clock by the primary PLL (F
Unimplemented: Read as ‘0’
GSWTRG: Global Software Trigger bit
When this bit is set by the user, it will trigger conversions if selected by the TRGSRC<4:0> bits in the
ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e., this
bit is not auto-clearing).
Unimplemented: Read as ‘0’
FORM: Data Output Format bit
1 = Fractional (D
0 = Integer (D
EIE: Early Interrupt Enable bit
1 = Interrupt is generated after first conversion is completed
0 = Interrupt is generated after second conversion is completed
ORDER: Conversion Order bit
1 = Odd numbered analog input is converted first, followed by conversion of even numbered input
0 = Even numbered analog input is converted first, followed by conversion of odd numbered input
SEQSAMP: Sequential Sample Enable bit
1 = Shared Sample and Hold (S&H) circuit is sampled at the start of the second conversion if
0 = Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
ORDER
R/W-0
U-0
ORDER = 0. If ORDER = 1, then the shared S&H is sampled at the start of the first conversion.
currently busy with an existing conversion process. If the shared S&H is busy at the time the
dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion
cycle.
—
ADCON: A/D CONTROL REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
SEQSAMP
OUT
ADSIDL
OUT
R/W-0
R/W-0
= 0000 00dd dddd dddd)
= dddd dddd dd00 0000)
(1)
ASYNCSAMP
(1)
(1)
SLOWCLK
(1)
R/W-0
R/W-0
Preliminary
VCO
(1)
(1)
(1)
)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
GSWTRG
R/W-0
R/W-0
ADCS<2:0>
x = Bit is unknown
R/W-1
U-0
—
DS70318D-page 245
(1)
FORM
R/W-0
R/W-1
bit 8
bit 0
(1)