atmega32u4-16mu ATMEL Corporation, atmega32u4-16mu Datasheet - Page 297

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atmega32u4-16mu

Manufacturer Part Number
atmega32u4-16mu
Description
Atmega32u4 8-bit Avr Microcontroller With 32k Bytes Of Isp Flash And Usb Controller
Manufacturer
ATMEL Corporation
Datasheet
7766A–AVR–03/08
• 7-4 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 3 - RSTCPU - USB Reset CPU bit
Set this bit to 1 by firmware in order to reset the CPU on the detection of a USB End of Reset
signal (without disabling the USB controller and Attached state). This bit is reset when the USB
controller is disabled, but is not affected by the CPU reset generated after a USB End of Reset
(remains enabled).
• 2 - LSM - USB Device Low Speed Mode Selection
When configured USB is configured in device mode, this bit allows to select the USB the USB
Low Speed or Full Speed Mod.
Clear to select full speed mode (D+ internal pull-up will be activate with the ATTACH bit will be
set).
Set to select low speed mode (D- internal pull-up will be activate with the ATTACH bit will be
set). This bit has no effect when the USB interface is configured in HOST mode.
• 1- RMWKUP - Remote Wake-up Bit
Set to send an “upstream-resume” to the host for a remote wake-up (the SUSPI bit must be set).
Cleared by hardware when signalling finished. Clearing by software has no effect.
See Section 23.10, page 289 for more details.
• 0 - DETACH - Detach Bit
Set to physically detach de device (disconnect internal pull-up on D+ or D-).
Clear to reconnect the device. See Section 23.9, page 288 for more details.
• 7 - Reserved
The value read from this bits is always 0. Do not set this bit.
• 6 - UPRSMI - Upstream Resume Interrupt Flag
Set by hardware when the USB controller is sending a resume signal called “Upstream
Resume”. This triggers an USB interrupt if UPRSME is set.
Shall be cleared by software (USB clocks must be enabled before). Setting by software has no
effect.
• 5 - EORSMI - End Of Resume Interrupt Flag
Set by hardware when the USB controller detects a good “End Of Resume” signal initiated by
the host. This triggers an USB interrupt if EORSME is set.
Shall be cleared by software. Setting by software has no effect.
• 4 - WAKEUPI - Wake-up CPU Interrupt Flag
Bit
Read/Write
Initial Value
7
0
-
UPRSMI
6
0
EORSMI
5
0
WAKEUPI
4
0
EORSTI
3
0
SOFI
2
0
ATmega32U4
1
0
-
SUSPI
0
0
UDINT
297

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