atmega32u4-16mu ATMEL Corporation, atmega32u4-16mu Datasheet - Page 136

• Manufacturer Part Number: atmega32u4-16mu
• Description: Atmega32u4 8-bit Avr Microcontroller With 32k Bytes Of Isp Flash And Usb Controller
• Manufacturer: ATMEL Corporation

14.10.17 Timer/Counter1 Interrupt Mask Register – TIMSK1
14.10.18 Timer/Counter3 Interrupt Mask Register – TIMSK3
14.10.19 Timer/Counter1 Interrupt Flag Register – TIFR1
136
ATmega32U4
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See “Interrupts” on page
7
–
R
0
7
–
R
0
7
–
R
0
(See “Interrupts” on page
(See “Interrupts” on page
(See “Interrupts” on page
6
–
R
0
6
–
R
0
6
–
R
0
59.) is executed when the TOVn Flag, located in TIFRn, is set.
5
ICIE1
R/W
0
5
ICIE3
R/W
0
5
ICF1
R/W
0
59.) is executed when the ICFn Flag, located in TIFRn, is set.
4
–
R
0
4
–
R
0
4
–
R
0
59.) is executed when the OCFnC Flag, located in
59.) is executed when the OCFnB Flag, located in
59.) is executed when the OCFnA Flag, located in
3
OCIE1
C
R/W
0
3
OCIE3
C
R/W
0
3
OCF1C
R/W
0
2
OCIE1B
R/W
0
2
OCIE3B
R/W
0
2
OCF1B
R/W
0
R/W
R/W
1
OCF1A
R/W
0
1
OCIE1A
0
1
OCIE3A
0
0
TOV1
R/W
0
0
TOIE1
R/W
0
0
TOIE3
R/W
0
TIFR1
TIMSK1
TIMSK3
7766A–AVR–03/08