atmega32u4-16mu ATMEL Corporation, atmega32u4-16mu Datasheet - Page 279

• Manufacturer Part Number: atmega32u4-16mu
• Description: Atmega32u4 8-bit Avr Microcontroller With 32k Bytes Of Isp Flash And Usb Controller
• Manufacturer: ATMEL Corporation

22.5.3
22.6
22.7
7766A–AVR–03/08
Speed Control
Memory management
Freeze clock
The firmware has the ability to reduce the power consumption by setting the FRZCLK bit, which
freeze the clock of USB controller. When FRZCLK is set, it is still possible to access to the fol-
lowing registers:
Moreover, when FRZCLK is set, only the following interrupts may be triggered:
The speed selection (Full Speed or Low Speed) depends on the D+/D- pull-up. The LSM bit in
UDCON register allows to select an internal pull up on D+ (Low Speed mode) or D- (Full Speed
mode) data lines.
Figure 22-11. Device mode Speed Selection
The controller only supports the following memory allocation management.
The reservation of a Pipe or an Endpoint can only be made in the increasing order (Pipe/End-
point 0 to the last Pipe/Endpoint). The firmware shall thus configure them in the same order.
The reservation of a Pipe or an Endpoint “k
ware allocates the memory and inserts it between the Pipe/Endpoints “k
Pipe/Endpoint memory “slides” up and its data is lost. Note that the “k
point memory does not slide.
Clearing a Pipe enable (PEN) or an Endpoint enable (EPEN) does not clear either its ALLOC bit,
or its configuration (EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should clear
ALLOC. Then, the “k
and upper Pipe/Endpoint memory does not slide.
• USBCON, USBSTA, USBINT
• UDCON (detach, ...)
• UDINT
• UDIEN
• WAKEUPI
• VBUSTI
UCAP
D+
D-
i+1
” Pipe/Endpoint memory automatically “slides” down. Note that the “k
i
” is done when its ALLOC bit is set. Then, the hard-
DETACH
UDCON.0
UDCON.2
LSM
Regulator
USB
ATmega32U4
i+2
i-1
” and upper Pipe/End-
” and “k
i+1
”. The “k
279
i+1
i+2
”
”