tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 47
tmp86fh46bng
Manufacturer Part Number
tmp86fh46bng
Description
8 Bit Microcontroller Tlcs-870/c Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP86FH46BNG.pdf
(216 pages)
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Part Number:
TMP86FH46BNG
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2.3
2.3.1
set, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and
the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during
the maximum 24/fc[s] (The RESET pin outputs "L" level).
ized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5μs at 16.0 MHz) when pow-
er is turned on. RESET pin outputs "L" level during maximum 24/fc[s] (1.5μs at 16.0MHz).
Reset Circuit
The TMP86FH46BNG has four types of reset generation procedures: An external reset input, an address trap re-
The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial-
Table 2-3 shows on-chip hardware initialization by reset action.
Table 2-3 Initializing Internal Status by Reset Action
Program counter
Stack pointer
General-purpose registers
(W, A, B, C, D, E, H, L, IX, IY)
Jump status flag
Zero flag
Carry flag
Half carry flag
Sign flag
Overflow flag
Interrupt master enable flag
Interrupt individual enable flags
Interrupt latches
age within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized.
the vector address stored at addresses FFFEH to FFFFH.
RESET
External Reset Input
The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.
When the RESET pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the power supply volt-
Whenthe RESET pin input goes high, the reset operation is released and the program execution starts at
On-chip Hardware
VDD
(IMF)
(PC)
(SP)
(CF)
(HF)
(ZF)
(SF)
(VF)
(EF)
(JF)
(IL)
Internal reset
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Figure 2-15 Reset Circuit
Initial Value
(FFFEH)
0
0
0
reset output
Malfunction
circuit
Page 29
Prescaler and divider of timing generator
Watchdog timer
Output latches of I/O ports
Control registers
RAM
On-chip Hardware
Watchdog timer reset
System clock reset
Address trap reset
Refer to I/O port circuitry
Refer to each of control
register
Not initialized
Initial Value
Enable
TMP86FH46BNG
0
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