tmp86fh46bng TOSHIBA Semiconductor CORPORATION, tmp86fh46bng Datasheet - Page 129
tmp86fh46bng
Manufacturer Part Number
tmp86fh46bng
Description
8 Bit Microcontroller Tlcs-870/c Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP86FH46BNG.pdf
(216 pages)
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Part Number:
TMP86FH46BNG
Manufacturer:
TOSHIBA/东芝
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SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK
SI pin
SIOSR<RXF>
INTSIO
interrupt
request
SIORDB
pin
(3)
Figure 10-10 Example of Internal Clock and MSB Receive Mode
tion is finished. Then INTSIO interrupt request is generated after SIOSR<RXERR> is set to “1”.
If received data is not read out from SIORDB receive error occurs immediately after shift opera-
There are two ways for stopping the receive operation.
Stopping the receive operation
・ The way of clearing SIOCR1<SIOS>.
・ The way of setting SIOCR1<SIOINH>.
A7
ta is finished to receive. When receive operation is finished, SIOSR<SIOF> is cleared to
“0”. In external clock operation, SIOCR1<SIOS> must be cleared to “0” before
SIOSR<SEF> is set to “1” by starting the next shift operation.
case, SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are initial-
ized.
A6 A5 A4 A3 A2 A1
When SIOCR1<SIOS> is cleared to “0”, receive operation is stopped after all of the da-
Receive operation is stopped immediately after SIOCR1<SIOINH> is set to “1”. In this
Start shift
operation
Automatic wait
A0
A
Writing transmit
data A
Page 111
B7 B6 B5 B4 B3 B2 B1
Start shift
operation
Writing transmit
data B
B0
B
C7
Start shift
operation
C6 C5 C4 C3 C2 C1 C0
Clearing SIOS
TMP86FH46BNG
Writing transmit
data C
C
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