dm93s62 Fairchild Semiconductor, dm93s62 Datasheet - Page 2

• Manufacturer Part Number: dm93s62
• Description: 9-input Parity Checker/generator
• Manufacturer: Fairchild Semiconductor

www.fairchildsemi.com
Functional Description
The DM93S62 is a very high speed 9-input parity checker
or generator. It is intended primarily for error detection in
systems which transmit data in 8-bit bytes, but it can be
expanded to any number of data inputs. Both even and odd
parity outputs are available to allow maximum flexibility for
both parity generation and parity checking. When the
device is enabled (E
is HIGH when an even number of inputs is HIGH, and the
Odd Parity output (PO) is HIGH when an odd number of
inputs is HIGH. The active LOW Enable (E) controls the
state of both outputs; when the Enable (E) is HIGH, both
outputs will be LOW. The Enable may be used to strobe the
outputs at very high speeds to synchronize or inhibit the
parity data.
The DM93S62 has been designed with two sections using
Exclusive-NOR comparison techniques. Eight data inputs
Data Inputs
Number of
3
4
5
6
7
8
LOW), the Even Parity output (PE)
TABLE 1. Termination Recommendations for Less than Nine Bits
D0
D0
D0
D0
D0
D0
FIGURE 1. Fast Input I8 allows Higher System Speed
I0
D1
D1
D1
I1
L
L
L
D1
D1
D1
D2
D2
D2
I2
D3
D3
D3
I3
2
L
L
L
I0–I7 represent one section which will generate a parity bit
in 16 ns to 20 ns. The ninth input (I8) bypasses three levels
of logic and switches the outputs in 6.0 ns to 9.0 ns. This
feature may be used to compensate for delayed arrival of
the parity bit, allowing faster system cycle times (Figure 1).
The fast I8 input is also useful when more than nine bits
are to be checked. The output of one DM93S62 drives the
I8 input of a second DM93S62, providing a 17-bit parity
check in 29 ns (typ).
When some inputs of the DM93S62 are not used, such as
for words of less than nine bits or when using parallel
expansion techniques, there is an optimum delay scheme
for termination of the unused inputs (see Table 1). In
essence, if one of the inputs of any Exclusive-NOR stays
HIGH, the delay from the other input to the output is mini-
mized.
D2
D2
D2
D4
D4
D4
I4
D5
I5
L
L
L
L
L
D3
D3
D5
D5
D6
I6
L
D7
I7
L
L
L
L
L
D4
D6
I8
L
L
L
L