tc58nvg0s3eta00 TOSHIBA Semiconductor CORPORATION, tc58nvg0s3eta00 Datasheet - Page 44

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tc58nvg0s3eta00

Manufacturer Part Number
tc58nvg0s3eta00
Description
1 Gbit 128m ? 8 Bit Cmos Nand E2prom
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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RY
/
BY
Data Cache
Page Buffer
Cell Array
A
A
Command
input
6
7
8
9
Page N + P1
8C
CA0 to CA11, PA0 to PA15
Copy Page address (M + R1) is input and if the data needs to be changed, changed data is input.
After programming of page M is completed, Data Cache for Page M + R1 is transferred to the Page Buffer.
By the 15h command, the data in the Page Buffer is programmed to Page M + R1. Data for Page N + P2 is transferred to the Data cache.
The data in the Page Buffer is programmed to Page M + Rn − 1. Data for Page N + Pn is transferred to the Data Cache.
Page M
6
(Page M+R1)
Address input
Address
Data for Page M + R1
6
Data input
When changing data,
changed data is input.
7
Data for Page M + R1
15
t
DCBSYW2
7
00
CA0 to CA11, PA0 to PA15
Page M + R1
Page N + P2
Address input
(Page N+P2)
Address
8
Data for Page N + P2
44
3A
t
DCBSYR2
Col = 0 start
Data output
8
Page M + Rn − 1
00
CA0 to CA11, PA0 to PA15
(Page N+Pn)
Address input
Address
Page N + Pn
9
TC58NVG0S3ETA00
Data for Page N + Pn
3A
t
DCBSYR2
9
Col = 0 start
Data output
2010-01-25C
Page M + Rn − 1
B
B

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