tc58nvg0s3eta00 TOSHIBA Semiconductor CORPORATION, tc58nvg0s3eta00 Datasheet - Page 35

• Manufacturer Part Number: tc58nvg0s3eta00
• Description: 1 Gbit 128m ? 8 Bit Cmos Nand E2prom
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(3) Notes
(a) Internal addressing in relation with the Districts
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(b) Address input restriction for the Multi Page Read operation
(Restriction)
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(60) [District 0, Page Address 0x0000] (60) [District 1, Page Address 0x0040] (30)
(60) [District 0, Page Address 0x0001] (60) [District 1, Page Address 0x0041] (30)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 0] (60) [District 1] (30)
(60) [District 1] (60) [District 0] (30)
It requires no mutual address relation between the selected blocks from each District.
(c)
Make sure
To use Multi Page Read operation, the internal addressing should be considered in relation with the District.
There are following restrictions in using Multi Page Read;
WP
The device consists from 2 Districts.
Each District consists from 512 erase blocks.
The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 1022
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 1023
signal
WP
is held to High level when Multi Page Read operation is performed
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TC58NVG0S3ETA00
2010-01-25C