74ALVC162374T Fairchild Semiconductor, 74ALVC162374T Datasheet

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74ALVC162374T

Manufacturer Part Number
74ALVC162374T
Description
IC FLIP FLOP 16BIT D 48TSSOP
Manufacturer
Fairchild Semiconductor
Series
74ALVCr
Type
D-Type Busr
Datasheet

Specifications of 74ALVC162374T

Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
200MHz
Delay Time - Propagation
3.9ns
Trigger Type
Positive Edge
Current - Output High, Low
12mA, 12mA
Voltage - Supply
1.65 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2001 Fairchild Semiconductor Corporation
74ALVC162374T
74ALVC162374
Low Voltage 16-Bit D-Type Flip-Flop
with 3.6V Tolerant Inputs and Outputs
and 26 Series Resistors in Outputs
General Description
The ALVC162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The ALVC162374 is also designed with 26
tors in the outputs. This design reduces line noise in appli-
cations such as memory address drivers, clock drivers and
bus transceivers/transmitters.
The 74ALVC162374 is designed for low voltage (1.65V to
3.6V) V
The 74ALVC162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
CC
applications with I/O compatibility up to 3.6V.
Package Number
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
series resis-
DS500688
Features
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
value of the resistor is determined by the current-sourcing capability of the
driver.
Pin Descriptions
Pin Names
OE
CP
I
O
0
1.65V–3.6V V
3.6V tolerant inputs and outputs
26 series resistors in outputs
t
Power-off high impedance inputs and outputs
Supports live insertion and withdrawal (Note 1)
Uses patented noise/EMI reduction circuitry
Latchup conforms to JEDEC JED78
ESD performance:
–I
0
PD
–O
n
n
15
3.9 ns max for 3.0V to 3.6V V
5.3 ns max for 2.3V to 2.7V V
9.6 ns max for 1.65V to 1.95V V
Human body model
Machine model
(CLK to O
15
Package Descriptions
n
CC
)
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
Outputs
supply operation
200V
CC
2000V
through a pull-up resistor; the minimum
October 2001
Revised October 2001
Description
CC
CC
CC
www.fairchildsemi.com

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74ALVC162374T Summary of contents

Page 1

... CMOS power dissipation. Ordering Code: Order Number Package Number 74ALVC162374T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © ...

Page 2

Connection Diagram Functional Description The 74ALVC162374 consists of sixteen edge-triggered flip- flops with individual D-type inputs and 3-STATE true out- puts. The device is byte controlled with each byte function- ing identically, but independent of the other. The control pins ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 3) 0. Input Diode Current ( Output Diode Current (I ) ...

Page 4

AC Electrical Characteristics Symbol Parameter V CC Min f Maximum Clock Frequency 250 MAX Propagation Delay PHL PL 1.3 Bus to Bus Output Enable Time 1.3 PZL PZH Output Disable Time ...

Page 5

AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3.3V 0. FIGURE 2. Waveform for Inverting and ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Body Width Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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