dm74s112 Fairchild Semiconductor, dm74s112 Datasheet
dm74s112
Manufacturer Part Number
dm74s112
Description
Dual Negative-edge-triggered Master-slave J-k Flip-flop With Preset, Clear, And Complementary Outputs
Manufacturer
Fairchild Semiconductor
Datasheet
1.DM74S112.pdf
(4 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
dm74s112N
Manufacturer:
NS/国半
Quantity:
20 000
© 2000 Fairchild Semiconductor Corporation
DM74S112
DM74S112
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. Data on the J and
K inputs can be changed while the clock is HIGH or LOW
without affecting the outputs as long as setup and hold
times are not violated. A low logic level on the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Ordering Code:
Connection Diagram
Order Number
Package Number
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006459
Function Table
H
X
L
Q
*
Toggle
0
established.
preset and/or clear inputs return to its inactive (HIGH) level.
each falling edge of the clock pulse.
This configuration is nonstable; that is, it will not persist when either the
LOW Logic Level
Negative going edge of pulse.
PR
Either LOW or HIGH Logic Level
HIGH Logic Level
H
H
H
H
H
H
L
L
The output logic level of Q before the indicated input conditions were
Package Description
Each output changes to the complement of its previous level on
CLR
H
H
H
H
H
H
L
L
Inputs
CLK
X
X
X
H
H
H
J
X
X
X
L
L
X
August 1986
Revised April 2000
K
X
X
X
H
H
X
L
L
www.fairchildsemi.com
Q
Q
Q
H
H
L
H*
L
0
0
Outputs
Toggle
Q
Q
Q
H
H*
H
L
L
0
0
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Datasheet:
dm74s112 Summary of contents
Page 1
... Ordering Code: Order Number Package Number DM74S112 N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram © 2000 Fairchild Semiconductor Corporation Package Description ...
Page 2
Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...
Page 3
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter V Input Clamp Voltage HIGH Level V OH Output Voltage V V LOW Level V OL Output Voltage V I Input Current @ Max ...
Page 4
Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at ...