mk50h27 STMicroelectronics, mk50h27 Datasheet - Page 6
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
mk50h27
Manufacturer Part Number
mk50h27
Description
Signalling System 7 Link Controller
Manufacturer
STMicroelectronics
Datasheet
1.MK50H27.pdf
(56 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mk50h27N
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
mk50h27Q-10
Manufacturer:
ST
Quantity:
12 388
Company:
Part Number:
mk50h27Q-25
Manufacturer:
ST
Quantity:
12 388
Company:
Part Number:
mk50h27Q33B
Manufacturer:
NIC
Quantity:
2 028
Company:
Part Number:
mk50h27Q33B
Manufacturer:
STMicroelectronics
Quantity:
10 000
MK50H27
SECTION 3
OPERATIONAL DESCRIPTION
The SGS-Thomson MK50H27 Multi-Logical Link
Communications Controller device is a VLSI prod-
uct intended for high performance data communi-
cation applications requiring SDLC link level con-
trol. The MK50H27 will perform all frame
formatting, such as: frame delimiting with flags,
FCS (CRC) generation and detection, and zero
bit insertion and deletion for transparency. The
MK50H27 also handles all supervisory (S) and
unnumbered (U) frames (see Tables A & B). The
MK50H27 also includes a buffer management
mechanism that allows the user to transmit and/or
receive multiple frames for each active channel
or DLCI. Contained in the buffer management is
an on-chip dual channel DMA: one channel for re-
ceive and one channel for transmit.
6/56
Table 1: PIN DESCRIPTION (continued)
SIGNAL NAME
VSS-GND
A<23:16>
SYSCLK
RESET
RCLK
TCLK
DTR
DSR
VCC
RTS
CTS
RD
TD
[37-43]
PIN(S)
32-39
[1,26]
1,24
[25]
[28]
[29]
[30]
[31]
[32]
[33]
[34]
[52]
23
25
26
27
28
29
30
31
48
TYPE
O/3S
IO
IO
O
I
I
I
I
I
As a Bus Slave, the MK50H27 asserts READY when it has put data on the
DAL lines during a READ cycle or is about to take data from the DAL lines
during a WRITE cycle. READY is a response to DAS and it will be released
after DAS or CS is negated.
RESET is the Bus signal that will cause MK50H27 to cease operation, clear
its internal logic and enter an idle state with the Stop bit of CSR0 set.
TRANSMIT CLOCK. A 1x clock input for transmitter timing. TD changes on
the falling edge of TCLK. The frequency of TCLK may not be greater than
the frequency of SYSCL
DATA TERMINAL READY, REQUEST TO SEND. Modem control pin. Pin
26 is configurable through CSR5. This pin can be programmed to behave as
output RTS or as programmable IO pin DTR. If configured as RTS, the
MK50H27 will assert this pin if it has data to send and throughout the
transmission of a signal unit.
RECEIVE CLOCK. A 1x clock input for receiver timing. RD is sampled on
the rising edge of RCLK. The frequency of RCLK may not be greater than
the frequency of SYSCLK.
SYSTEM CLOCK. System clock used for internal timing of the MK50H27.
SYSCLK should be a square wave, of frequency up to 33 MHz.
TRANSMIT DATA. Transmit serial data output.
DATA SET READY, CLEAR TO SEND. Modem Control Pin. Pin 30 is
configurable through CSR5. This pin can be programmed to behave as input
CTS or as programmable IO pin DSR. If configured as CTS, the MK50H27
will transmit all ones while CTS is high.
RECEIVE DATA. Received serial data input.
Address bits <23:16> used in conjunction with DAL<15:00> to produce a 24
bit address. MK50H27 drives these lines only as a Bus Master. A23-A20
may be driven continuously as described in the CSR4<7> BAE bit.
Ground Pins
Power Supply Pin
+5.0 VDC + 5%
The MK50H27 can be used with any popular 16
or 8 bit microprocessor. A possible system con-
figuration for the MK50H27 is shown in Figure 1.
This document assumes that the processor has a
byte addressable memory organization.
The MK50H27 will move multiple blocks of re-
ceive and transmit data directly in and out of
memory through the Host’s bus.
The MK50H27 may be operated in full or half du-
plex mode. In half duplex mode the RTS and
CTS modem control pins are provided. In full du-
plex mode, these pins become user programma-
ble I/O pins.
All signal pins on the MK50H27 are TTL compat-
ible.
MK50H27 independent of the physical interface.
As shown in Fig. 1, line drivers and receivers are
used for electrical connection to the physical
layer.
This has the advantage of making the
DESCRIPTION