mk50h27 STMicroelectronics, mk50h27 Datasheet - Page 36

• Manufacturer Part Number: mk50h27
• Description: Signalling System 7 Link Controller
• Manufacturer: STMicroelectronics

MK50H27
4.3.2 Transmit Message Descriptor Entry
4.3.2.1 Transmit Message Descriptor 0 (TMD0)
4.3.2.2 Transmit Message Descriptor 1 (TMD1)
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BIT
15
14
13
12
11:08
11:10
07:00
BIT
15:00
OWNA
OWNB
SLF
ELF
0
PRIN
TBADR
NAME
TBADR
NAME
1
5
O
W
N
A
1
5
1
4
O
W
N
B
1
4
1
3
S
L
F
1
3
owns this descriptor. When this bit is a one the MK50H27 owns this
descriptor. The host sets the OWNA bit after filling the buffer pointed
to by the descriptor entry. The MK50H27 releases the descriptor after
transmitting
ledgement from the receiver. After the MK50H27, Host, or I/O ac-
celeration processor has relinquished ownership of a buffer, it may not
change any field in the four words that comprise the descriptor entry.
bit. This bit is provided to facilitate use of a Layer 3 I/O processor.
MK50H27 for this signal unit. It is used for data chaining buffers. SLF
is set by the Host. When not chaining, SLF should be set to a one.
NOTE: A ”Long Signal Unit” is any MSU which needs data chaining.
MK50H27 for this signal unit. It is used for data chaining buffers. If
both SLF and ELF were set the signal unit would fit into one buffer
and no data chaining would be required. ELF is set by the Host.
When not chaining, ELF should be set to a one.
transmitted frame when JSS7E=1 (TTC JT-Q703 compliant mode).
This field is written by the Host and unchanged by MK50H27.
TBADR is written by the Host and unchanged by MK50H27.
least significant bit is zero since the descriptor must be word aligned.
DESCRIPTION
When this bit is a zero either the HOST or the SLAVE PROCESSOR
This bit determines whether the Host or the Layer 3 I/O Processor owns
Start of Long Signal Unit indicates that this is the first buffer used by the
End of Long Signal Unit indicates that this is the last buffer used by the
Reserved, must be written as zeroes for CCITT/ITU operation.
These bits determine the content of the Priority Indication bits of the
The High Order 8 address bits of the buffer pointed to by this descriptor.
DESCRIPTION
The Low Order 16 address bits of the buffer pointed to by this descriptor
the buffer when OWNA is a zero.
1
2
E
L
F
1
2
1
1
1
1
PRIN
1
0
1
0
the buffer
TBADR<15:00>
0
9
0
0
9
0
8
0
0
8
0
7
0
7
and
0
6
0
6
TBADR<23:16>
0
5
0
5
receiving
The MK50H27 never uses this
0
4
0
4
0
3
0
3
0
2
0
2
the
0
1
0
1
proper acknow-
0
0
0
0
0
The