mk50h27 STMicroelectronics, mk50h27 Datasheet - Page 20

• Manufacturer Part Number: mk50h27
• Description: Signalling System 7 Link Controller
• Manufacturer: STMicroelectronics

MK50H27
4.1.2.3 Control and Status Register 2 (CSR2)
RAP<3:1> = 2
4.1.2.4 Control and Status Register 3 (CSR3)
RAP<3:1> = 3
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BIT
15
14
13
12
11:09
08
07:00
BIT
15:00
NAME
CYCLE
ESEN
0
RSUTE
0
JSS7E
IADR
NAME
IADR
1
5
C
Y
C
L
E
1
5
1
4
E
S
E
N
1
4
1
3
0
1
3
1
2
R
S
U
T
E
1
2
the receipt of an MSU after having entered congestion. This primitive
indicates that the remote node congestion has abated.
or 5 vs 7 SYSCLKs for single DMA). See Figures 7a and 8a for details.
timer pre-scaler at IADR+24 rather than the 8-bit Scaler at IADR+02.
Using the 16-bit Scaler allows longer timer values at higher SYSCLK
rates. Set ESEN=0 for backward compatibility with the MK50H27.
more than 32xTP time between received Signal Units. If RSUTE=1,
PPRIM=5 will be issued upon expiry of the Received SU Timer. A typi-
cal use for RSUT is to detect breaking of the serial data connection.
When JSS7E=1 the MK50H27 will align using only SIEs, timers Tf, Ts,
To, Ta, and Te will be activated appropriately, and the SUERM will act
in accordance with JT-Q703 requiring interchanging the location of the
T and D fields in the Initialization Block. If JSS7E=1 the MK50H27 will
NOT comply with all CCITT/ITU, ANSI, or AT&T specifications.
in the Initialization Block.
prior to issuing an INIT primitive.
in the Initialization Block. Must be written by the Host prior to issu-
ing an INIT primitive. The Initialization block must begin on a word
boundary.
DESCRIPTION
Setting this bit selects a shorter DMA cycle (5 vs 6 SYSCLKs for bursting
Extended Scaler Enable. Setting this bit enables the use of the 16-bit
Reserved, must be written as zeroes.
Received SU Timer Enable. Setting this bit enables a timer for detecting
Reserved, must be written as zeroes.
Japanese SS7 Enable. Setting this bit enables TTC JT-Q703 compliance.
The high order 8 bits of the address of the first word (lowest address)
DESCRIPTION
The low order 16 bits of the address of the first word (lowest address)
1
1
0
1
1
1
0
0
1
0
IADR <15:00>
0
9
0
0
9
0
8
J
S
S
7
E
0
8
0
7
0
7
0
6
0
6
0
5
0
5
IADR<23:16>
IADR must be written by the Host
0
4
0
4
0
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0