mk50h27 STMicroelectronics, mk50h27 Datasheet
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mk50h27
Manufacturer Part Number
mk50h27
Description
Signalling System 7 Link Controller
Manufacturer
STMicroelectronics
Datasheet
1.MK50H27.pdf
(56 pages)
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SECTION 1 - FEATURES
September 1997
and Bellcore Signalling System Number 7 link
level protocols.
TTC JT-Q703 specification requirements
MK50H25 (X.25/LAPD), MK50H29 (SDLC),
and MK50H28(Frame Relay).
33), or 25 MHz (MK50H27 - 25).
protocol processing, 20 Mbps for transparent
HDLC mode, or up to 51 Mbps bursted
(gapped data clocks, non-continuous data).
length.
ing optional 5 SYSCLK DMA cycle (150 nS) at
33 MHz SYSCLK.
ods, including forced retransmission for PCR.
Signal Unit interval timers for Japanese SS7.
(number of flags between SU’s)
Programmable Watchdog Timers for RCLK
and TCLK (to detect absence of data clocks)
Complete Level 2 Implementation of SS7.
Compatible with 1988 CCITT, AT&T, ANSI,
Optional operation to comply with Japanese
Pin-for-pin and architecturally compatible with
System clock rates up to 33 MHz (MK50H27 -
Data rate up to 4 Mbps continuous for SS7
On chip DMA control with programmable burst
DMA transfer rate of up to 13.3 Mbytes/sec us-
Buffer Management includes:
Selectable BEC or PCR retransmission meth-
Handles all 7 SS7 Timers, plus the additional
Handles all SS7 frame formatting:
Programmable minimum Signal Unit spacing
Handles all sequencing and link control.
Selectable FCS of 16 or 32 bits.
Testing Facilities:
Programmable for full or half duplex operation
- Initialization Block
- Separate Receive and Transmit Rings
- Variable Descriptor Ring and Window Sizes.
- Zero bit insert and delete
- FCS generation and detection
- Frame delimiting with flags
- Internal Loopback
- Silent Loopback
- Optional Internal Data Clock Generation
- Self Test.
SECTION 2 - INTRODUCTION
The SGS - Thomson SS7 Signalling Link Control-
ler (MK50H27) is a VLSI semiconductor device
which provides a complete level 2 data communi-
cation control conforming to the CCITT, ANSI,
BELLCORE, and AT&T versions of SS7, as well
as options to allow conformance to TTC JT-Q703
(Japanese SS7). This includes signal unit format-
ting, transparency (so-called ”bit-stuffing”), error
recovery by two types of retransmission, error
monitoring, sequence number control, link status
control, and fill in signal unit generation.
One of the outstanding features of the MK50H27
is its buffer management which includes on-chip
DMA. This feature allows users to handle multi-
ple MSU’s of receive and transmit data at a time.
(A conventional data link control chip plus a sepa-
rate DMA chip would handle data for only a single
block at a time.) The MK50H27 will move multiple
blocks of receive and transmit data directly into
Available in 52 pin PLCC, 84 pin PLCC(for use
with external ROM), or 48 pin DIP packages.
Signalling System 7
PLCC 52
DIP48
Link Controller
MK50H27
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