mk50h27 STMicroelectronics, mk50h27 Datasheet - Page 22

no-image

mk50h27

Manufacturer Part Number
mk50h27
Description
Signalling System 7 Link Controller
Manufacturer
STMicroelectronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mk50h27N
Manufacturer:
ST
Quantity:
20 000
Part Number:
mk50h27Q-10
Manufacturer:
ST
Quantity:
12 388
Part Number:
mk50h27Q-10
Manufacturer:
ST
0
Part Number:
mk50h27Q-25
Manufacturer:
ST
Quantity:
12 388
Part Number:
mk50h27Q-25
Manufacturer:
ST
0
Part Number:
mk50h27Q-33
Quantity:
3 710
Part Number:
mk50h27Q-33
Manufacturer:
ST
0
Part Number:
mk50h27Q-33/25/16
Manufacturer:
ST
0
Part Number:
mk50h27Q33B
Manufacturer:
NIC
Quantity:
2 028
Part Number:
mk50h27Q33B
Manufacturer:
STMicroelectronics
Quantity:
10 000
MK50H27
22/56
04:03
02
01
00
BCON
BURST
BSWPD
ACON
”Non-data DMA transfers refers to any DMA transfers that access
memory other than the data buffers themselves. This includes the
Initialization Block, Descriptors, and Status Buffer. It has no effect
on data DMA transfers. BSWPC allows the MK50H27 to operate with
memory organizations that have bits 07:00 at even addresses and
with bits 15:08 at
Read/Write and cleared by BUS RESET.
With BSWPC = 1:
This memory organization is used with the 8086 family of microproces-
sors.
With BSWPC = 0:
This memory organization is used with the 68000 and the Z8000
microprocessors.
performed each time control of the host bus is obtained. BURST
is READ/WRITE and cleared on bus Reset.
Data transfers are those to or from a data buffer. BSWPD has no ef-
fect on non-data transfers. The effect of BSWPD on data transfers is
the same
above).
tems, this bit should be set.
MK50H27 is a Bus Master. ACON is READ/ WRITE and cleared by
Bus RESET.
BCON is READ/WRITE and cleared by Bus RESET.
This field determines the maximum number of data transfers
This bit determines the byte ordering of all data DMA transfers.
ALE CONTROL defines the assertive state of pin 18 when the
BYTE CONTROL redefines the Byte Mask and Hold I/O pins.
XX1
XX0
BCON
BURST <1:0>
Address
Address
* Suggested setting
ACON
0
1
0
8
0
1
10*
For most applications, including most 68000 based sys-
00
01
. . .
. . .
as
15
7
BUSAKO
that
PIN16
BM1
ASSERTED HIGH
ASSERTED LOW
odd addressses or
of BSWPC on non-data transfers
PIN18
8 bit mode
unlimited
16 bytes
XX1
2 bytes
PIN15
BYTE
XX1
BM0
Address
Address
0
8
. . .
. . . 15
NAME
ALE
vice versa.
AS
BUSRQ
7
PIN17
HOLD
16 bit mode
unlimited
1 words
8 words
BSWPC is
(see

Related parts for mk50h27