aduc7033bstz-8l-rl Analog Devices, Inc., aduc7033bstz-8l-rl Datasheet - Page 55

• Manufacturer Part Number: aduc7033bstz-8l-rl
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADC Configuration Register
Name:
Address:
Default Value:
Access:
Function:
Table 42. ADCCFG MMR Bit Designations
Bit
7
6, 5
4, 3
2
1
0
ADCCFG
0xFFFF051C
0x00
Read/write
The 8-bit ADC Configuration MMR controls extended functionality related to the on-chip ADCs.
Description
Analog Ground Switch Enable. Set to 1 by user software to connect the external GND_SW pin (Pin 15) to an internal
analog ground reference point. This bit can be used to connect and disconnect external circuits and components to
ground under program control and thereby minimize dc current consumption when the external circuit or component
is not being used. This bit is used in conjunction with ADCMDE[6] to select a 20 kΩ resistor to ground.
Current Channel (32-Bit) Accumulator Enable.
Current Channel ADC Comparator Enable.
Current Channel ADC Overrange Enable. Set by user to enable a coarse comparator on the Current Channel ADC. If the
current reading is grossly (>30% approximate) overrange for the active gain setting, then the overrange bit in the
ADCSTA MMR is set. The current must be outside this range for greater than 125 μs for the flag to be set. This feature
should not be used in ADC low power mode.
Not Used. This bit is reserved for future functionality and should be written as 0 by user code.
Current Channel ADC, Result Counter Enable. Set by user to enable the result count mode. In this mode, an I-ADC
interrupt is generated only when ADC0RCV = ADC0RCL. This allows the I-ADC to continuously monitor current but only
interrupt the MCU core after a defined number of conversions. The voltage/temperature ADC also continues to convert
if enabled, but again, only the last conversion result is available (intermediate V/T-ADC conversion results are not stored)
when the ADC counter interrupt occurs.
00 = accumulator disabled and reset to 0. The accumulator must be disabled for a full ADC conversion, (ADCSTA[0]
set twice) before the accumulator can be re-enabled to ensure the accumulator is reset.
01 = accumulator active.
10 = accumulator active.
11 = not defined.
00 = comparator disabled.
01 = comparator active, interrupt asserted if absolute value of I-ADC conversion result |I| ≥ ADC0TH.
10 = comparator count mode active, interrupt asserted if absolute value of an I-ADC conversion result |I| ≥ ADC0TH
for the number of ADC0TCL conversions. A conversion value |I| < ADC0TH resets the threshold counter value
(ADC0THV) to 0.
11 = comparator count mode active, interrupt asserted if absolute value of an I-ADC conversion result |I| ≥ ADC0TH
for the number of ADC0TCL conversions. A conversion value |I| < ADC0TH decrements the threshold counter value
(ADC0THV) towards 0.
Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for
>65,535 conversions.
Negative current values are subtracted from the accumulator total; the accumulator is clamped to a minimum
value of 0.
Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for
>65,535 conversions.
The absolute values of negative current are subtracted from the accumulator total; the accumulator in this mode
continues to accumulate negatively, below 0.
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ADuC7033