aduc7033bstz-8l-rl Analog Devices, Inc., aduc7033bstz-8l-rl Datasheet - Page 10
aduc7033bstz-8l-rl
Manufacturer Part Number
aduc7033bstz-8l-rl
Description
Integrated Precision Battery Sensor For Automotive
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADUC7033BSTZ-8L-RL.pdf
(136 pages)
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ADuC7033
TIMING SPECIFICATIONS
SPI Timing Specifications
Table 2. SPI Master Mode Timing (PHASE Mode = 1)
Parameter
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
t
t
HCLK
UCLK
depends on the clock divider or CD bits in PLLCON MMR. t
= 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
SCLK
SCLK
MOSI
MISO
1
1
t
DAV
t
SH
Figure 2. SPI Master Mode Timing (PHASE Mode = 1)
2
t
DSU
HCLK
2
MSB IN
= t
MSB
t
UCLK
DHD
t
Rev. 0 | Page 10 of 136
SL
/2
CD
t
.
DF
Min
0
3 × t
UCLK
t
DR
BITS [6:1]
BITS [6:1]
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
3.5
3.5
3.5
3.5
t
SR
HCLK
HCLK
t
LSB IN
SF
Max
(2 × t
LSB
UCLK
) + (2 × t
HCLK
)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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