aduc7033bstz-8l-rl Analog Devices, Inc., aduc7033bstz-8l-rl Datasheet - Page 23

• Manufacturer Part Number: aduc7033bstz-8l-rl
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time the request can take through
the synchronizer plus the time to enter the exception mode.
Note that the ARM7TDMI initially (first instruction) runs in
ARM (32-bit) mode when an exception occurs. The user can
immediately switch from ARM mode to Thumb mode if
required, for example, when executing interrupt service
routines.
MEMORY ORGANIZATION
The ARM7, a von Neumann architecture, MCU core sees
memory as a linear array of 2
Figure 13, the ADuC7033 maps this into four distinct user areas,
namely: a memory area that can be remapped, an SRAM area, a
Flash/EE area, and a memory mapped register (MMR) area.
•
•
•
•
Any access, either reading or writing, to an area not defined in
the memory map results in a data abort exception.
Memory Format
The ADuC7033 memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address.
The first 94 kB of this memory space is used as an area into
which the on-chip Flash/EE memory or SRAM can be
remapped.
The ADuC7033 features a second 4-kB area at the top of
the memory map used to locate the MMRs, through which
all on-chip peripherals are configured and monitored.
The ADuC7033 features a SRAM size of 6 kB.
The ADuC7033 features 96 kB of on-chip Flash/EE
memory. 94 kB of on-chip Flash/EE memory are available
to the user. In addition, 2 kB are reserved for the on-chip
kernel.
BIT 31
BYTE 3
B
7
3
.
.
.
BYTE 2
Figure 12. Little Endian Format
A
6
2
.
.
.
32 BITS
BYTE 1
9
5
1
.
.
.
32
byte locations. As shown in
BYTE 0
8
4
0
.
.
.
BIT 0
0xFFFFFFFF
0x00000004
0x00000000
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SRAM
The ADuC7033 features 6 kB of SRAM, organized as
1536 locations × 32 bits, that is, 1536 words, which is
located at 0x40000.
The RAM space can be used as data memory and also as
a volatile program space.
ARM code can run directly from SRAM at full clock speed
given that the SRAM array is configured as a 32-bit wide
memory array. SRAM is read/writeable in 8-, 16-, and 32-bit
segments.
Remap
The ARM exception vectors are situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020.
By default, after a reset, the Flash/EE memory is logically
mapped to Address 0x00000000.
It is possible to logically remap the SRAM to Address 0x00000000.
This is accomplished by setting Bit 0 of the SYSMAP0 MMR
located at 0xFFFF0220. To revert Flash/EE memory to
0x00000000, Bit 0 of SYSMAP0 is cleared.
It is sometimes desirable to remap RAM to 0x00000000
to optimize the interrupt latency of the ADuC7033 because
code can run in full 32-bit ARM mode and at maximum core
speed. Note that when an exception occurs, the core defaults to
ARM mode.
0xFFFF0000
0x00080000
0x00040000
0x00000000
0xFFFF0FFF
Figure 13. ADuC7033 Memory Map
0x00087FFF
0x00040FFF
0x00007FFF
RESERVED
MMRs
RESERVED
FLASH/EE
RESERVED
SRAM
RESERVED
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
ADuC7033