aduc7033bstz-8l-rl Analog Devices, Inc., aduc7033bstz-8l-rl Datasheet - Page 121

• Manufacturer Part Number: aduc7033bstz-8l-rl
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

LIN Hardware Synchronization Control Register 0
Name:
Address:
Default Value:
Access:
Function:
Table 94. LHSCON0 MMR Bit Designations
Bit
31 to 13
12
11
10
9
8
LHSCON0
0xFFFF0784
0x0000
Read/write
The LHS control register is a 32-bit register that, in conjunction with the LHSCON1 register, is used to configure the
LIN mode of operation.
Description
Reserved. These bits are reserved for future use and should be written as 0 by user software.
Rising Edge Detected Interrupt Disable.
Break Timer Compare Interrupt Disable.
Break Timer Error Interrupt Disable.
LIN Transceiver, Standalone Test Mode.
Gate UART/BSD R/W Bit.
BSD Mode.
LIN Mode.
Set to 1 to disable the break timer compare interrupt.
Cleared to 0 to enable the break timer compare interrupt.
Set to 1 to disable the break timer error interrupt.
Cleared to 0 to enable the break timer error interrupt.
Cleared to 0 by user code to operate the LIN in normal mode, it is driven directly from the on-chip UART.
Set to 1 by user code to enable external GPIO_7 and GPIO_8 pins to drive the LIN Transceiver TxD and LIN Transceiver
RxD, respectively, independent of the UART. The functions of GPIO_7 and GPIO_8 should first be configured by user
code via the GPIO function select Bit 0 and Bit 4 in the GP2CON register.
Set to 1 by user code to disable the internal UART RxD (receive data) by gating it high until both the break field and
subsequent LIN sync byte have been detected. This ensures the UART does not receive any spurious serial data during
break or sync field periods that have to be flushed out of the UART before valid data fields can be received.
Set to 0 by user code to enable the internal UART RxD (receive data) after the break field and subsequent LIN sync
byte have been detected so that the UART can receive the subsequent LIN data fields.
In BSD mode, LHSCON0[6] is set to 1. Because of the finite propagation delay in the BSD transmit (from the MCU to
the external pin) and receive (from the external pin to the MCU) paths, user code must not switch between BSD write
and read modes until the MCU confirms the external BSD pin is deasserted. Failure to adhere to this recommendation
can result in the generation of an inadvertent break condition interrupt after user code switches from BSD write
mode to BSD read mode. A stop condition interrupt can be used to ensure that this scenario is avoided.
In BSD read mode, this bit is set to 1 by user code to enable the generation of a break condition interrupt (LHSSTA[0])
on a rising edge of the BSD bus. In BSD read mode, the break timer (LHSVAL1) starts counting on the falling edge
and stops counting on the rising edge. The generation of an interrupt on this rising edge allows user code to deter-
mine if a 0, 1, or a sync pulse width has been received. It should also be noted that the break timer still generates
an interrupt if the value in the LIN break timer (LHSVAL1 read value) equals the break timer compare value (LHSVAL1
write value), and if the break timer overflows. This configuration can be used in BSD read mode to detect fault
conditions on the BSD bus.
In BSD write mode, this bit is cleared to 0 by user code to disable the generation of break condition interrupts on a
rising edge of the BSD bus (as is required in BSD read mode). In BSD write mode, the LHS compare interrupt (LHSSTA[3])
is used to determine when the MCU should release the BSD bus when transmitting data. If the break condition
interrupt was still enabled, it would generate an unwanted interrupt as soon as the BSD bus is deasserted. As in
BSD read mode, the break timer stops counting on a rising edge, so the break timer can also be used in this mode
to allow user code to confirm the pulse width in transmitted data bits.
Set to 1 to disable the rising edge detected interrupt.
Cleared to 0 to enable the break rising edge detected interrupt.
Set to 1 to enable the rising edge detected interrupt.
Cleared to 0 to disable the break rising edge detected interrupt.
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ADuC7033