sta015t STMicroelectronics, sta015t Datasheet - Page 34
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sta015t
Manufacturer Part Number
sta015t
Description
Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
Manufacturer
STMicroelectronics
Datasheet
1.STA015T.pdf
(44 pages)
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STA015-STA015B-STA015T
The STA015 contains 56 consecutive 8-bit regis-
ters corresponding to the maximum number of
ancillary data that may be contained in MPEG
frame. The ANCCOUNT_L and ANCOUNT_H
registers contain the number of ancillary data bits
available within the current MPEG frame.
To perform ancillary data reading a status regis-
ter (0xB6 - INTERRUPT_STATUS_REGISTER)
is available: bit 0 of this register should be polled
by the microcontroller in order to understand
when new data are available.
5.3. I/O CELL DESCRIPTION (pinout relative to TQFP44 package)
1) CMOS Tristate Output Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 2, 4, 13, 27, 33, 42, 44
2) CMOS Bidir Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 3, 31
3) CMOS Inpud Pad Buffer / Pin numbers 24, 26, 32, 34, 36, 40
4) CMOS Inpud Pad Buffer with Active Pull-Up / Pin numbers 22, 25, 28, 38
5) CMOS Schmitt Trigger Bidir Pad Buffer with active Pull-up, 4mA, with slew rate control /
34/44
Pin numbers 14, 16, 18, 20, 35, 37, 39, 41, 43
A
EN
EN
ZI
A
A
A
EN
ZI
A
D98AU905
D00AU1150
D98AU907
D98AU904
IO
D98AU906
Z
IO
Z
Z
INPUT PIN CAPACITANCE
INPUT PIN CAPACITANCE
IO
IO
0x7E
0xB5
0xB6
----
----
----
----
OUTPUT PIN
INPUT PIN
INPUT PIN
Z
A
A
5pF
5pF
ANC_DATA_56
ANC_DATA_1
OUTPUT
OUTPUT
---------
---------
---------
---------
CAPACITANCE
CAPACITANCE
ISR
PIN
PIN
IO
IO
MAX LOAD
100pF
3.5pF
3.5pF
LOAD
100pF
LOAD
100pF
MAX
MAX