sta015t STMicroelectronics, sta015t Datasheet - Page 19

• Manufacturer Part Number: sta015t
• Description: Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
• Manufacturer: STMicroelectronics

ADPCM_DATA BUFFER
Address: 0x40 - 0x51 (64 - 81)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
ANCCOUNT_L
Address: 0x41 (65)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
ANCCOUNT_H
Address: 0x42 (66)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
ANCCOUNT_H
ANCCOUNT registers are logically concatenated
and indicate the number of Ancillary Data bits
available at every correctly decoded MPEG
frame.
HEAD_H[23:16]
x = don’t care
HEAD_M[15:8]
MSB
AC15 AC14 AC13 AC12 AC11 AC10 AC9
MSB
MSB
MSB
MSB
AC7
H15
b7
b7
b7
b7
b7
X
b6
AC6
H14
b6
b6
b6
b6
X
ENCODED DATA N to N+18
b5
AC5
H13
b5
b5
b5
b5
X
b4
AC4
H20
H12
b4
b4
b4
b4
b3
AC3
H1‘1
H19
b3
b3
b3
b3
b2
AC2
H18
H10
b2
b2
b2
b2
b1
AC1
H17
H9
b1
b1
b1
b1
LSB
b0
LSB
AC0
LSB
AC8
LSB
LSB
H16
H8
b0
b0
b0
b0
HEAD_L[7:0]
Address: 0x43, 0x44, 0x45 (67, 68, 69)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
Head[1:0] emphasis
Head[2] original/copy
Head[3] copyrightHead
[5:4] mode extension
Head[7:6] mode
Head[8] private bit
Head[9] padding bit
Head[11:10] sampling frequency index
Head[15:12] bitrate index
Head[16] protection bit
Head[18:17] layer
Head[19] ID
Head[20] ID_ex
The HEAD registers can be viewed as logically
concatenated to store the MPEG Layer III Header
content. The set of three registers is updated
every time the synchronisation to the new MPEG
frame is achieved
The meaning of the flags are shown in the follow-
ing tables:
MPEG IDs
Layer
in Layer III these two flags must be set always to
”01”.
Protection_bit
It equals ”1” if no redundancy has been added
and ”0” if redundancy has been added.
MSB
H7
b7
IDex
0
0
1
1
H6
b6
H5
b5
STA015-STA015B-STA015T
H4
b4
ID
0
1
0
1
H3
b3
H2
b2
MPEG 2.5
reserved
MPEG 2
MPEG 1
H1
b1
LSB
19/44
H0
b0