sta015t STMicroelectronics, sta015t Datasheet - Page 33

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sta015t

Manufacturer Part Number
sta015t
Description
Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
Manufacturer
STMicroelectronics
Datasheet

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0
ADPCM_FRAME_SIZE
Address: 0xBD (189)
Type: R/W
Software Reset: 0x13
Hardware Reset: 0x00
The ADPCM frame size may be adjusted to
match a trade-off between the bitrate overhead
and the frame length. The frame size (in bytes) is
calculated as follow:
FRAME size = (ADPCM_FRAME_SIZE * 90)
+108
The frame starts with a 5 bytes sync word
(0x5354445649) and, after that, a frame header:
- 13 bytes for DVI algorithm
- 103 bytes for G726 pack algorithms
ADPCM_INT_CFG
Address: 0xBE (190)
Type: R/W
Software Reset: 0x0B
Hardware Reset: 0x00
Using this register the ADPCM interrupt capability
can be properly configured.
AFS7 AFS6 AFS5 AFS4 AFS3 AFS2 AFS1 AFS1
MSB
MSB
INTL
INTL0 -
INTL6
b7
b7
6
INTL
b6
b6
5
Interrupt Length
The interrupt length can be programmed,
using this bits, from 0 up to 128 system
clock cycles
INTL
b5
b5
4
INTL
b4
b4
3
INTL
b3
b3
2
INTL
b2
b2
1
INTL
b1
b1
0
LSB
LSB
b0
b0
X
GPIO_CONF
Address: 0xBF (191)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
This register controls how data are strobed on the
GPIO interface.
ADC_WLEN
Address: 0xC0 (192)
Type: R/W
Software Reset: 0x0F
Hardware Reset: 0x0F
To select ADC word length AWL4 through AWL0
bits can be used. This 5 bit value must contain
the size of the significant data bits minus one.
ADC_WPOS
Address: 0xC1 (193)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
These bits specify the position of the sample
word referred to the LRCK slot boundary. Bit
AWP0 thru AWP4 must be programmed with the
number of bits to ignore after the sample word.
MSB
MSB
MSB
GOSP:
b7
b7
GISP:
b7
X
X
X
b6
b6
X
X
b6
X
GPIO Strobe Polarity in INPUT mode
0 =
1 =
GPIO Strobe Polarity in OUTPUT mode
0 =
1 =
b5
b5
X
X
b5
X
AWL4 AWL3 AWL2 AWL1 AWL0
AWL4 AWL3 AWL2 AWL1 AWL0
data strobed an falling edge
data strobed on rising edge
non inverted
inverted
STA015-STA015B-STA015T
b4
b4
b4
X
b3
b3
b3
X
b2
X
b2
b2
GOSP
b1
b1
b1
GISP
LSB
LSB
LSB
b0
33/44
b0
b0

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