sta015t STMicroelectronics, sta015t Datasheet - Page 25

• Manufacturer Part Number: sta015t
• Description: Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
• Manufacturer: STMicroelectronics

PCMCONF
Address: 0x55 (85)
Type: R/W
Software Reset: 0x21
Hardware Reset: 0x21
PCMCONF is used to set the PCM Output Inter-
face configuration:
ORD: PCM order. If this bit is set to’1’, the LS Bit
is transmitted first, otherwise MS Bit is transmiited
first.
DIF: PCM_DIFF. It is used to select the position
of the valid data into the transmitted word. This
setting is significant only in 18/20/24 bit/word
mode.If it is set to ’0’ the word is right-padded,
otherwise it is left-padded.
INV (fig.13): It is used to select the LRCKT clock
polarity. If it is set to ’1’ the polarity is compliant to
I2S format (low -> left , high -> right), otherwise
the LRCKT is inverted. The default value is ’0’. (if
I2S have to be selected, must be set to ’1’ in the
STA015 configuration phase).
Figure 19. LRCKT Polarity Selection
FOR: FORMAT is used to select the PCM Output
Interface format.
After hw and sw reset the value is set to 0 corre-
sponding to I
SCL (fig.14): used to select the Transmitter Serial
Clock polarity. If set to ’1’ the data are sent on the
LRCKT
LRCKT
MSB
b7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ORD
b6
left
left
1
0
2
S format.
DIF
b5
0
1
right
right
INV
b4
1
0
left
left
FOR
b3
0
1
INV_LRCLK=0
INV_LRCLK=1
SCL
b2
1
0
PREC (1) PREC (1)
b1
0
0
1
1
rising edge of SCKT and sampled on the falling. If
set to ’0’ , the data are sent on the falling edge
and sampled on the rising. This last option is the
most commonly used by the commercial DACs.
The default configuration for this flag is ’0’.
Figure 20. SCKT Polarity Selection
PREC [1:0]: PCM PRECISION
It is used to select the PCM samples precision, as
follows:
’00’: 16 bit mode (16 slots transmitted)
’01’: 18 bit mode (32 slots transmitted)
’10’: 20 bit mode (32 slots transmitted)
’11’: 24 bit mode (32 slots transmitted)
The PCM samples precision in STA015 can be
16 or 18-20-24 bits.
When STA015 operates in 16 (18-20-24) bits
mode, the number of bits transmitted during a
LRCLT period is 32 (64).
LSB
b0
0
1
0
1
SCKT
SDO
SCKT
SDO
Data are sent on the rising edge of SCKT
PCM order the MS bit is transmitted First
PCM order the LS bit is transmitted First
Data are sent on the falling edge of SCKT
LRCKT Polarity compliant to I2S format
INV_SCLK=0
INV_SCLK=1
STA015-STA015B-STA015T
16 bit mode (16 slots transmitted)
18 bit mode (18 slots transmitted)
20 bit mode (20 slots transmitted)
24 bit mode (24 slots transmitted)
The word is right padded
LRCKT Polarity inverted
The word is left padded
Different formats
Description
I2S format
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