sta015t STMicroelectronics, sta015t Datasheet - Page 11

• Manufacturer Part Number: sta015t
• Description: Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
• Manufacturer: STMicroelectronics

Figure 10.
To enable the GPSO interface bit GEN of
GPSO_ENABLE register must be set. Using the
GPSO_CONF register the protocol can be config-
ured in order to provide outcoming data on ris-
ing/falling edge of GPSO_SCKR input clock; the
GPSO_REQ request signal polarity (usually con-
nected to an MCU interrupt line) can be config-
ured as well.
ADC Inteface
Beside the serial input interface based on SDI
and SCKR lines a 3 wire flexible and user config-
urable input interface is also available, suitable to
interface with most A/D converters. To configure
this interface 4 specific I
(ADC_ENABLE, ADC_CONF, ADC_WLEN and
ADC_WPOS). Refer to registers description for
more details.
General Purpose I/O Interface
A new general purpose I/O interface has been
added to this device (TQFP44 and LFBGA64
only). Actually only the strobe line is used in
(*) STA013 Compatible mode
Figure. 11
ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC)
ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC)
SERIAL I/F (SCKR + SDI + DATA_REQ)
SERIAL I/F (SCKR + SDI + DATA_REQ) (*)
INPUT (data to encode)
2
C registers are available
LRCK_ADC
DATA_REQ
SCK_ADC
SDI_ADC
SCKR
SDI
GPSO_SCKR
GPSO_DATA
GPSO_REQ
RECEIVER
ADC I/F
SERIAL
STA015
GPSO I/F (GPSO_REQ + GPSO_DATA +
GPSO_SCKR)
I
GPSO I/F (GPSO_REQ + GPSO_DATA +
GPSO_SCKR)
I
MUX
2
2
C + Interrupt (SCL + SDA + DATA_REQ)
C (polling) (SCL + SDA)
GPSO_SCKR
GPSO_DATA
GPSO_REQ
ENCOD
ENGINE
ADPCM to provide an interrupt; the use of the
other bits is still to be defined. The related con-
figuration register is GPIO_CONF. See the follow-
ing summary for related pin usage:
2.5 ADPCM Encoding: Overview
According to the previously described interfaces
there are 4 ways to manage ADPCM data stream
while encoding. Input interface can be either the
serial receiver block (SDI + SCKR + DATA_REQ
lines) or the ADC specific interface.
Output interfaces can be either the I
or without interrupt line) or the GPSO high-speed
serial interface (GPSO_REQ + GPSO_ DATA +
GPSO_SCKR lines). This result in the following 4
methods to handle encoding flow:
Output (encoded data)
I/ODATA [0]
....................
I/ODATA [7]
GPIO_STROBE
Name
MCU
D99AU1064
GPSO
I
2
C
D00AU1145
STA015-STA015B-STA015T
GPSO_REQ
GPSO_DATA
GPSO_SCKR
SDA
SCL
DATA_REQ
GPIO strobe line
GPIO data line
Description
SO28/TQFP44
SO28/TQFP44
Available on
LFBGA64
LFBGA64
LFBGA64
LFBGA64
2
package
TQFP44
TQFP44
C bus (with
Dir
I/O
I/O
I/O
....
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