ptn3392 NXP Semiconductors, ptn3392 Datasheet - Page 8

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ptn3392

Manufacturer Part Number
ptn3392
Description
2-lane Displayport To Vga Adapter Ic
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
PTN3392
Product data sheet
7.3.1 PTN3392 specific DPCD register settings
7.3 DPCD registers
DPCD registers that are part of the VESA DisplayPort v1.1a are described in detail in
Ref.
The PTN3392 DisplayPort receiver capability and status information about the link are
reported by DisplayPort Configuration Data (DPCD) registers, when a DisplayPort source
issues a read command on the AUX CH. The DisplayPort source device can also write to
the link configuration field of DPCD to configure and initialize the link. The DPCD is
DisplayPort v1.1a compliant.
It is the responsibility of the host to only issue commands within the capability of the
PTN3392 as defined in the ‘Receiver Capability Field’ in order to prevent undefined
behavior. PTN3392 specific DPCD registers are listed in
Table 3.
DPCD
register
Receiver Capability Field
0000Bh
0000Ch
Link Configuration Field
00109h
1. The following paragraphs only describe the specific implementation by PTN3392.
[1]
PTN3392 specific DPCD registers
Description
RECEIVE_PORT1_CAP_1. ReceiverPort1 Capability_1.
I
this register are assigned to I
Bits 7:0
I
Bit values in this register are assigned to I
as follows:
Bits 7:0
See also behavior of pin S2 in
2
2
C-bus speed control capabilities bit map. The bit values in
C-bus speed control/status bit map.
0000 0001b = 1 kbit/s; supported by PTN3392
0000 0010b = 3 kbit/s; supported by PTN3392
0000 0100b = 10 kbit/s; supported by PTN3392
0000 1000b = 100 kbit/s; supported by PTN3392
0001 0000b = 400 kbit/s; not supported by PTN3392
0010 0000b = 1 Mbit/s; not supported by PTN3392
0100 0000b = reserved
1000 0000b = reserved
0000 0001b = 1 kbit/s; supported by PTN3392
0000 0010b = 3 kbit/s; supported by PTN3392
0000 0100b = 10 kbit/s; supported by PTN3392
0000 1000b = 100 kbit/s; supported by PTN3392
0001 0000b = 400 kbit/s; not supported by PTN3392
0010 0000b = 1 Mbit/s; not supported by PTN3392
0100 0000b = reserved
1000 0000b = reserved
Default value: 0000 1000b (100 kbit/s)
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 July 2010
2
C-bus speeds as follows:
Table
2.
2
2-lane DisplayPort to VGA adapter IC
C-bus speeds
Table
3.
Power-on
Reset
value
00h
0Fh
S2 setting
PTN3392
© NXP B.V. 2010. All rights reserved.
Read/write
over
AUX CH
read only
read only
read/write
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