ptn3392 NXP Semiconductors, ptn3392 Datasheet - Page 17

• Manufacturer Part Number: ptn3392
• Description: 2-lane Displayport To Vga Adapter Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
12. Characteristics
Table 7.
Table 8.
[1]
[2]
PTN3392
Product data sheet
Symbol
I
I
P
R
R
R
Symbol
UI
Δf
V
t
t
t
V
I
L
f
DD
DD(stb)
RX_EYE_CONN
RX_EYE_CHIP
RX_EYE_m-mJT_CHP
RX_SHORT
RX_TRACKING_BW
RX_SKEW
RX_DIFFp-p
RX_DC_CM
th(j-a)
PU
pd
DOWN_SPREAD
Range is nominal ±350 ppm. DisplayPort link RX does not require local crystal for link clock generation.
Up to 0.5 % down spread is supported. Modulation frequency range of 30 kHz to 33 kHz must be supported.
Current consumption, power dissipation and thermal characteristics
DisplayPort receiver main link characteristics
Parameter
supply current
standby supply current
power dissipation
thermal resistance from junction
to ambient
pull-up resistance
pull-down resistance
12.1 Current consumption, power dissipation and thermal characteristics
12.2 DisplayPort receiver main link
Parameter
unit interval
link clock down spreading
differential input peak-to-peak
voltage
receiver eye time at RX-side
connector pins
receiver eye time at RX
package pins
time between jitter median and
maximum median deviation
(package pins)
RX DC common mode voltage
RX short-circuit current limit
total skew
jitter tracking bandwidth
All information provided in this document is subject to legal disclaimers.
normal operation,
normal operation,
Conditions
UXGA / 162 MHz pixel clock
Standby mode
UXGA / 162 MHz pixel clock
in free air for SOT619-1
RESET_N pin; 0 V ≤ V
S0 to S3 pins; 0 V ≤ V
Rev. 2 — 15 July 2010
Conditions
for high bit rate
(2.7 Gbit/s per lane)
for low bit rate
(1.62 Gbit/s per lane)
at RX package pins
for high bit rate
for reduced bit rate
for high bit rate
for reduced bit rate
for high bit rate
for reduced bit rate
at RX package pins
lane intra-pair skew at RX
package pins;
inter-pair; lane-to-lane skew
for high bit rate
for reduced bit rate
for high bit rate
for reduced bit rate
I
I
≤ V
≤ V
DD
DD
2-lane DisplayPort to VGA adapter IC
[4][5]
[4][5]
[4][5]
[10]
-
Min
-
-
-
44
44
[1]
[1]
[2]
[3]
[3]
[4]
[4]
[4]
[6]
[7]
[8]
[9]
[9]
Min
-
-
0.0
120
40
0.51
0.25
0.47
0.22
-
-
0
-
-
-
-
20
Typ
180
12
600
35
66
66
Typ
370
617
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PTN3392
© NXP B.V. 2010. All rights reserved.
Max
-
-
-
-
95
95
Max
-
-
0.5
-
-
-
-
-
-
0.265
0.39
2.0
50
5200
100
300
-
17 of 29
Unit
mA
mA
mW
K/W
kΩ
kΩ
Unit
ps
ps
%
mV
mV
UI
UI
UI
UI
UI
UI
V
mA
ps
ps
ps
MHz