ptn3392 NXP Semiconductors, ptn3392 Datasheet - Page 10

• Manufacturer Part Number: ptn3392
• Description: 2-lane Displayport To Vga Adapter Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PTN3392
Product data sheet
7.3.2.1 I
7.3.2.2 I
7.3.2 I
7.4 Monitor detection
Bit or bits are set to indicate I
DisplayPort source reads register 0000Ch and sets the I
DPCD register 00109h setting. The PTN3392 then adapts its I
set by the DisplayPort source.
Bit values in this register are assigned to I
Prior to software writing to this register, PTN3392 defaults to the I
100 kbit/s or 10 kbit/s) selected by the S2 pin
On read, the PTN3392 returns a value set to indicate the speed currently in use.
On write, software provides a mask to limit the speeds to be enabled:
Some specific examples are listed below for clarification purposes:
For DDC communication, the PTN3392 generates defer responses to the source while the
I
when the I
I2C_ACK takes 9 ms. Given this, the DisplayPort source should expect over
20 I2C_DEFER’s when requesting to read a byte over I
The PTN3392 assumes 75 Ω double termination, as shown in
circuit of the PTN3392 senses a 37.5 Ω or 75 Ω termination respectively, when the
monitor is connected or disconnected. The load-sensing circuit is active during the vertical
blanking period (never during the horizontal retrace period), so that there will be no
disturbance to the screen image caused by the load-sensing circuit.
Upon detection of an RGB monitor being connected, the PTN3392 dynamically updates
DPCD register 00200h and 00204h, to indicate the presence of a sink device being
connected (see
generates an IRQ request on HPD.
2
2
2
2
C-bus speed control register (read only, 0000Ch)
C-bus speed control/status register (read/write, 00109h)
•
•
•
•
•
C-bus transfer is taking place as specified in the DisplayPort standard v1.1a. Note that
C over AUX CH registers
The PTN3392 uses the slowest speed enabled by the mask and the PTN3392 speed
capabilities.
If the result of the mask with the speed capabilities is 0000 0000b, then the PTN3392
keeps the S2 setting I
change).
If the source writes 1111 1111b, the PTN3392 uses the lowest speed of 1 kbit/s.
If the source writes 0000 1100b, the PTN3392 uses the lower of 10 kbit/s and
100 kbit/s, i.e., 10 kbit/s.
If the source writes 0011 0000b, the PTN3392 would stay using the same I
speed that it is using before the software write (i.e., no change).
2
C-bus bit rate is set to 1 kbit/s, each bit takes 1 ms. One byte including
All information provided in this document is subject to legal disclaimers.
Section
Rev. 2 — 15 July 2010
7.3). After updating the DPCD register 00200h, the PTN3392
2
C-bus speed that it is using before the software write (i.e., no
2
C-bus speed control capabilities.
2
C-bus speeds.
(Table
2-lane DisplayPort to VGA adapter IC
2).
2
2
C-bus at the slowest rate.
C-bus speed according to the
2
Figure
C-bus bit rate to the speed
2
C-bus speed (either
6. The load sensing
PTN3392
© NXP B.V. 2010. All rights reserved.
2
C-bus
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