ptn3392 NXP Semiconductors, ptn3392 Datasheet - Page 18

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ptn3392

Manufacturer Part Number
ptn3392
Description
2-lane Displayport To Vga Adapter Ic
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Minimum CDR tracking bandwidth at the receiver when the input is repetition of D10.2 symbols without scrambling.
Table 9.
[1]
[2]
[3]
[4]
[5]
PTN3392
Product data sheet
Symbol
UI
N
t
t
V
R
V
V
I
C
AUX_BUS_PARK
jit(cc)
AUX_SHORT
AUX_DIFFp-p
AUX_DC_CM
AUX_TURN_CM
PRECHARGE_PULSES
AUX_TERM(DC)
AUX
Informative; refer to
t
1 − t
Common mode voltage is equal to V
Total drive current of the input bias circuit when it is shorted to its ground.
Maximum skew limit between different RX lanes of a DisplayPort link.
Maximum skew limit between D+ and D− of the same lane.
Results in the bit rate of 1 Mbit/s including the overhead of Manchester II coding.
Each pulse is a ‘0’ in Manchester II code.
Period after the AUX CH STOP condition for which the bus is parked.
Maximum allowable UI variation within a single transaction at connector pins of a transmitting device. Equal to 24 ns maximum. The
transmitting device is a source device for a request transaction and a sink device for a reply transaction.
Maximum allowable UI variation within a single transaction at connector pins of a receiving device. Equal to 30 ns maximum. The
transmitting device is a source device for a request transaction and a sink device for a reply transaction.
RX_EYE_m-mJT_CHP
RX_EYE_CONN
DisplayPort receiver AUX CH characteristics
12.3 DisplayPort receiver AUX CH
specifies the allowable Total Jitter (TJ).
specifies the total allowable Deterministic Jitter (DJ).
Figure 7
Parameter
unit interval
number of precharge pulses
AUX CH bus park time
cycle-to-cycle jitter time
AUX differential peak-to-peak
voltage
AUX CH termination DC resistance informative
AUX DC common-mode voltage
AUX turnaround common-mode
voltage
AUX short-circuit current limit
AUX AC coupling capacitor
Fig 7.
for definition of differential voltage.
pre-emphasis = 20Log(V
Definitions of pre-emphasis and differential voltage
bias_RX
All information provided in this document is subject to legal disclaimers.
voltage.
V
V
V
CM
D+
D−
Rev. 2 — 15 July 2010
DIFF_PRE
Conditions
AUX
transmitting device
receiving device
transmitting device
receiving device
/ V
DIFF
)
V
DIFF_PRE
2-lane DisplayPort to VGA adapter IC
[10]
V
[1]
[2]
[3]
[4]
[5]
[6]
[6]
[7]
[8]
[9]
DIFF
Min
0.4
10
10
-
-
0.39
0.32
-
0
-
-
75
002aaf363
100
Typ
0.5
-
-
-
-
-
-
-
-
-
-
PTN3392
© NXP B.V. 2010. All rights reserved.
Max
0.6
16
-
0.04
0.05
1.38
1.36
-
2.0
0.4
90
200
18 of 29
Unit
μs
ns
UI
UI
V
V
Ω
V
V
mA
nF

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