ptn3392 NXP Semiconductors, ptn3392 Datasheet - Page 5

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ptn3392

Manufacturer Part Number
ptn3392
Description
2-lane Displayport To Vga Adapter Ic
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
PTN3392
Product data sheet
Table 2.
Symbol
DisplayPort
ML0_P
ML0_N
ML1_P
ML1_N
AUX_P
AUX_N
HPD
RGB DAC outputs
BLU
BLU_N
GRN
GRN_N
RED
RED_N
RSET
DDC
SCL
SDA
Monitor-side sync
HSYNC
VSYNC
JTAG
TCK
TDO
TMS
TRST_N
TDI
Pin description
All information provided in this document is subject to legal disclaimers.
Pin
43
44
46
47
39
40
3
16
19
21
20
25
24
22
11
13
15
14
5
6
8
9
10
Rev. 2 — 15 July 2010
Type
self-biasing
differential input
self-biasing
differential input
self-biasing
differential input
self-biasing
differential input
self-biasing
differential
input/output
self-biasing
differential
input/output
3.3 V TTL
single-ended output
analog output
analog output
analog output
analog output
analog output
analog output
analog input/output
single-ended 5 V
open-drain DDC I/O
single-ended 5 V
open-drain DDC I/O
single-ended 3.3 V
TTL output
single-ended 3.3 V
TTL output
input
output
input
input
input
…continued
‘green’ current analog output
‘green’ current complementary analog output
‘red’ current complementary analog output
Description
DisplayPort main lane signal lane 0, positive
DisplayPort main lane signal lane 0, negative
DisplayPort main lane signal lane 1, positive
DisplayPort main lane signal lane 1, negative
DisplayPort auxiliary channel signal, positive
DisplayPort auxiliary channel signal, negative
Hot-plug detect
‘blue’ current analog output
‘blue’ current complementary analog output
‘red’ current analog output
DAC full-scale current control resistor.
Pull down to ground by an external
1.2 kΩ ± 1 % resistor.
5 V sink-side DDC clock I/O. Pulled up by
1.2 kΩ external resistor to 5 V.
5 V sink-side DDC data I/O. Pulled up by
1.2 kΩ external resistor to 5 V.
horizontal sync signal to monitor; serial
resistance of 36 Ω is recommended.
vertical sync signal to monitor; serial
resistance of 36 Ω is recommended.
JTAG clock input
JTAG data output
JTAG mode select input
JTAG reset (active LOW) input
JTAG data input
2-lane DisplayPort to VGA adapter IC
PTN3392
© NXP B.V. 2010. All rights reserved.
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