cyv15g0204trb Cypress Semiconductor Corporation., cyv15g0204trb Datasheet - Page 23

• Manufacturer Part Number: cyv15g0204trb
• Description: Independent Clock Hotlink Ii Dual Serializer And Dual Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02101 Rev. *B
CYV15G0204TRB AC Electrical Characteristics
PLL Characteristics
CYV15G0204TRB TRGCLKx Switching Characteristics Over the Operating Range
f
t
t
t
t
t
t
t
CYV15G0204TRB Bus Configuration Write Timing Characteristics Over the Operating Range
t
t
t
CYV15G0204TRB JTAG Test Clock Characteristics Over the Operating Range
f
t
CYV15G0204TRB Device RESET Characteristics Over the Operating Range
t
CYV15G0204TRB Transmitter and Reclocker Serial Output Characteristics Over the Operating Range
t
t
t
CYV15G0204TRB Transmitter Output PLL Characteristics
t
t
t
CYV15G0204TRB Reclocker Output PLL Characteristics
t
t
CYV15G0204TRB Receive PLL Characteristics Over the Operating Range
t
t
Notes:
24. While sending BIST data at the corresponding data rate, after 10,000 histogram hits, time referenced to REFCLKx± input.
25. Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide-bandwidth digital sampling oscilloscope. The
REF
REFCLK
REFH
REFL
REFD
REFR
REFF
REFRX
DATAH
DATAS
WRENP
TCLK
TCLK
RST
B
RISE
FALL
JTGENSD
JTGENHD
TXLOCK
JRGENSD
JRGENHD
RXLOCK
RXUNLOCK
Parameter
Parameter
Parameter
measurement was recorded after 10,000 histogram hits, time referenced to REFCLKx± of the transmit channel.
[16]
[16]
[16, 17, 18, 19]
[22]
[16, 17, 18, 19]
[23]
[16, 24]
[16, 24]
[16, 25]
[16, 25]
Transmit Jitter Generation - SD Data Rate
Transmit Jitter Generation - HD Data Rate
Transmit PLL lock to REFCLKx±
Reclocker Jitter Generation - SD Data Rate
Reclocker Jitter Generation - HD Data Rate
Receive PLL lock to input data stream (cold start)
Receive PLL lock to input data stream
Receive PLL Unlock Rate
TRGCLKx Clock Frequency
TRGCLKx Period = 1/f
TRGCLKx HIGH Time (TXRATEx = 1)(Half Rate)
TRGCLKx HIGH Time (TXRATEx = 0)(Full Rate)
TRGCLKx LOW Time (TXRATEx = 1)(Half Rate)
TRGCLKx LOW Time (TXRATEx = 0)(Full Rate)
TRGCLKx Duty Cycle
TRGCLKx Rise Time (20%–80%)
TRGCLKx Fall Time (20%–80%)
TRGCLKx Frequency Referenced to Received Clock Frequency
Bus Configuration Data Hold
Bus Configuration Data Setup
Bus Configuration WREN Pulse Width
JTAG Test Clock Frequency
JTAG Test Clock Period
Device RESET Pulse Width
Bit Time
CML Output Rise Time 20−80% (CML Test Load)
CML Output Fall Time 80−20% (CML Test Load)
Description
Description
REF
Description
(continued)
REFCLKx = 27 MHz
REFCLKx = 148.5 MHz
TRGCLKx = 27 MHz
TRGCLKx = 148.5 MHz
SPDSELx = HIGH
SPDSELx= MID
SPDSELx =LOW
SPDSELx = HIGH
SPDSELx = MID
SPDSELx =LOW
Condition
Condition
Min.
CYV15G0204TRB
2.9
2.9
–0.15
Min.
Min.
19.5
100
660
180
100
180
5.9
5.9
6.6
10
10
50
30
50
50
30
0
[16]
[16]
Typ.
200
133
107
76
51.28
+0.15
Max.
5128
1000
1000
Max.
376k
376k
Max
270
500
200
150
270
500
70
20
46
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2
2
Unit
ps
ps
µs
ps
ps
UI
UI
UI
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
%
%
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