cyv15g0204trb Cypress Semiconductor Corporation., cyv15g0204trb Datasheet - Page 16

• Manufacturer Part Number: cyv15g0204trb
• Description: Independent Clock Hotlink Ii Dual Serializer And Dual Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02101 Rev. *B
Static Latch Values
There are some latches in the table that have a static value
(i.e., 1, 0, or X). The latches that have a ‘1’ or ‘0’ must be
Table 4. Device Configuration and Control Latch Descriptions
TXCKSELA
TXCKSELB
TXRATEA
TXRATEB
TXBISTA
TXBISTB
TOE2A
TOE2B
TOE1A
TOE1B
PABRSTA
PABRSTB
RXRATEC
RXRATED
SDASEL1C[1:0]
SDASEL1D[1:0]
Name
Transmit Clock Select. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock
source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input register
TXDx[9:0] is clocked by REFCLKx↑. In this mode, the phase alignment buffer in the transmit path is bypassed.
When TXCKSELx = 0, the associated TXCLKx↑ is used to clock in the input register TXDx[9:0].
Transmit PLL Clock Rate Select. The initialization value of the TXRATEx latch = 0. TXRATEx is used to
select the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the
associated REFCLKx± input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the TXCLKOx
output clocks are full-rate clocks and follow the frequency and duty cycle of the associated REFCLKx± input.
When TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx± input by 20 to generate the
serial bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice the frequency rate of the
REFCLKx± input. When TXCLKSELx = 1 and TXRATEx = 1, the Transmit Data Inputs are captured using
both the rising and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx = LOW, is an invalid state and
this combination is reserved.
Transmit Bist Disabled. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit
BIST is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When TXBISTx = 0,
the transmit BIST function is enabled.
Secondary Differential Serial Data Output Driver Enable. The initialization value of the TOE2x latch = 0.
TOE2x selects if the TOUTx2± secondary differential output drivers are enabled or disabled. When TOE2x =
1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter.
When TOE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via the
configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel
are in this disabled state, the associated internal logic for that channel is also powered down. A device reset
(RESET sampled LOW) disables all output drivers.
Primary Differential Serial Data Output Driver Enable. The initialization value of the TOE1x latch = 0.
TOE1x selects if the TOUTx1± primary differential output drivers are enabled or disabled. When TOE1x = 1,
the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter.
When TOE1x = 0, the associated serial data output driver is disabled. When a driver is disabled via the
configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel
are in this disabled state, the associated internal logic for that channel is also powered down. A device reset
(RESET sampled LOW) disables all output drivers.
Transmit Clock Phase Alignment Buffer Reset. The initialization value of the PABRSTx latch = 1. The
PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx is
written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized.
PABRST is an asynchronous input, but is sampled by each TXCLKx↑ to synchronize it to the internal clock
domain. PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete the
initialization of the Phase Alignment Buffer.
Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx is used to select
the rate of the RXCLKx± clock output.
When RXRATEx = 1, the RXCLKx± clock outputs are complementary clocks that follow the recovered clock
operating at half the character rate. Data for the associated receive channels should be latched alternately
on the rising edge of RXCLKx+ and RXCLKx–.
When RXRATEx = 0, the RXCLKx± clock outputs are complementary clocks that follow the recovered clock
operating at the character rate. Data for the associated receive channels should be latched on the rising edge
of RXCLKx+ or falling edge of RXCLKx–.
Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the SDASEL1x[1:0]
latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the INx1± Primary
Differential Serial Data Inputs.
When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled.
When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.
When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.
When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.
Signal Description
configured with their corresponding value each time that their
associated latch bank is configured. The latches that have an
‘X’ are don’t cares and can be configured with any value.
CYV15G0204TRB
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