cyv15g0204trb Cypress Semiconductor Corporation., cyv15g0204trb Datasheet - Page 22

• Manufacturer Part Number: cyv15g0204trb
• Description: Independent Clock Hotlink Ii Dual Serializer And Dual Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02101 Rev. *B
CYV15G0204TRB AC Electrical Characteristics
t
t
t
t
f
t
t
CYV15G0204TRB Receiver LVTTL Switching Characteristics Over the Operating Range
f
t
t
t
t
t
t
f
t
t
CYV15G0204TRB REFCLKx Switching Characteristics Over the Operating Range
f
t
t
t
t
t
t
t
t
t
Notes:
17. The ratio of rise time to falling time must not vary by greater than 2:1.
18. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
19. All transmit AC timing parameters measured with 1-ns typical rise time and fall time.
20. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
21. Receiver UI (Unit Interval) is calculated as 1/(f
22. The duty cycle specification is a simultaneous condition with the t
23. TRGCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
TXCLKR
TXCLKF
TXDS
TXDH
TOS
TXCLKO
TXCLKOD
RS
RXCLKP
RXCLKD
RXCLKR
RXCLKF
RXDv–
RXDv+
ROS
RECLKO
RECLKOD
REF
REFCLK
REFH
REFL
REFD
REFR
REFF
TREFDS
TREFDH
REFRX
Parameter
cycle cannot be as large as 30%–70%.
TRGCLKx± must be within ±1500 PPM (±0.15%) of the transmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver channel
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.
[16, 17, 18, 19]
[22]
[16, 17, 18, 19]
[20]
[20]
[23]
[16, 17, 18, 19]
[16, 17, 18, 19]
[16]
[16]
TXCLKx Rise Time
TXCLKx Fall Time
Transmit Data Set-up Time to TXCLKx↑ (TXCKSELx = 0)
Transmit Data Hold Time from TXCLKx↑ (TXCKSELx = 0)
TXCLKOx Clock Frequency = 1x or 2x REFCLKx Frequency
TXCLKOx Period=1/f
TXCLKO Duty Cycle centered at 60% HIGH time
RXCLKx± Clock Output Frequency
RXCLKx± Period = 1/f
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate)
RXCLKx± Rise Time
RXCLKx± Fall Time
Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 0)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1)
RECLKOx Clock Frequency
RECLKOx Period=1/f
RECLKOx Duty Cycle centered at 60% HIGH time
REFCLKx Clock Frequency
REFCLKx Period = 1/f
REFCLKx HIGH Time (TXRATEx = 1)(Half Rate)
REFCLKx HIGH Time (TXRATEx = 0)(Full Rate)
REFCLKx LOW Time (TXRATEx = 1)(Half Rate)
REFCLKx LOW Time (TXRATEx = 0)(Full Rate)
REFCLKx Duty Cycle
REFCLKx Rise Time (20%–80%)
REFCLKx Fall Time (20%–80%)
Transmit Data Set-up Time to REFCLKx - Full Rate
(TXRATEx = 0, TXCKSELx = 1)
Transmit Data Set-up Time to REFCLKx - Half Rate
(TXRATEx = 1, TXCKSELx = 1)
Transmit Data Hold Time from REFCLKx - Full Rate
(TXRATEx = 0, TXCKSELx = 1)
Transmit Data Hold Time from REFCLKx - Half Rate
(TXRATEx = 1, TXCKSELx = 1)
TRGCLKx Frequency Referenced to Received Clock Period
REF
TOS
ROS
* 20) (when TRGRATEx = 1) or 1/(f
RS
REF
Description
REFH
and t
(continued)
REFL
REF
parameters. This means that at faster character rates the REFCLKx± duty
* 10) (when TRGRATEx = 0). In an operating link this is equivalent to t
5UI–2.0
5UI–1.3
5UI–1.8
5UI–2.6
CYV15G0204TRB
2.9
2.9
–0.15
Min.
19.5
6.66
–1.9
9.75
6.66
–1.0
19.5
6.66
19.5
-1.9
0.2
0.2
0.3
0.3
5.9
2.2
1.0
6.6
5.9
2.4
2.3
1.0
1.6
30
[16]
[16]
[21]
[21]
[21]
[21]
102.56
51.28
51.28
51.28
+0.15
+1.0
Max
150
150
150
150
1.7
1.7
1.2
1.2
70
Page 22 of 30
0
0
2
2
MHz
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
B
.
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